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authorWerner Almesberger <werner@almesberger.net>2016-06-30 01:55:02 (GMT)
committerWerner Almesberger <werner@almesberger.net>2016-06-30 01:55:02 (GMT)
commit936514977a96daf86a04792f4908c0d1a0d2492a (patch)
tree63b5ed43a74c59b5b0409f20c4a2532c987fadb4 /ir
parent12392eedbf69fac22124d4e99cce85cd8f416963 (diff)
downloadmisc-936514977a96daf86a04792f4908c0d1a0d2492a.zip
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ir/: add section about the configuration logic
Diffstat (limited to 'ir')
-rw-r--r--ir/Makefile8
-rw-r--r--ir/ir.spell4
-rw-r--r--ir/ir.tex59
-rw-r--r--ir/logic.fig187
4 files changed, 138 insertions, 120 deletions
diff --git a/ir/Makefile b/ir/Makefile
index 623fe9c..cc9b1cc 100644
--- a/ir/Makefile
+++ b/ir/Makefile
@@ -1,13 +1,17 @@
-FIGS = sys filter cir irda uart window chamber rx
+BIBDIR = ../bib
+
+FIGS = sys filter cir irda uart window chamber rx logic
.PHONY: all spell clean
.SUFFIXES: .fig .pdf
NAME = ir
-all: $(NAME).tex $(FIGS:%=%.pdf)
+all: $(NAME).tex $(FIGS:%=%.pdf) $(NAME).bbl
pdflatex $(NAME)
+include $(BIBDIR)/Makefile.bib
+
spell: _tmp.spell
sed -e 's/\\url{[^}]*}//g' -e '/%.*/d' $(NAME).tex | \
ispell -t -l -W 2 -p _tmp.spell | \
diff --git a/ir/ir.spell b/ir/ir.spell
index 091c41f..4e23e36 100644
--- a/ir/ir.spell
+++ b/ir/ir.spell
@@ -1,5 +1,6 @@
# Own names
Qucs
+Silego
# Language
behaviour
@@ -18,6 +19,7 @@ Neo
Hackerbus
# Fragments of component names
+SLG
VEMD
VSMB
@@ -30,10 +32,12 @@ IrDA
OOK
PCB
PWM
+SIM
SMT
# Parts of signal names
CTS
+INV
MDR
REG
RRXINVERT
diff --git a/ir/ir.tex b/ir/ir.tex
index 82f4d19..030430c 100644
--- a/ir/ir.tex
+++ b/ir/ir.tex
@@ -8,6 +8,7 @@
% non-ragged indentation of footnotes; send to bottom
\usepackage{footnote}
%\usepackage[hidelinks,bookmarks=true]{hyperref}
+\usepackage[numbib]{tocbibind} % add references to PDF TOC
\usepackage[hidelinks,bookmarksnumbered=true,bookmarksopen]{hyperref}
% Copyright notice in the footer (first page only)
@@ -296,6 +297,7 @@ section \ref{irrx}.
% -----------------------------------------------------------------------------
\section{Configurations}
+\label{cfg}
The IR subsystem can be configured for several different modes of operation.
The following sections detail the various configurations.
@@ -455,6 +457,7 @@ at least one of the following must be true:
% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
\subsection{Mode summary}
+\label{modesum}
\def\unspec{---}
\def\outpos{$\stackrel{\strut\sqcap}{\longrightarrow}$}
@@ -640,6 +643,55 @@ IR subsystem must be pulled to a safe state.
% -----------------------------------------------------------------------------
+\section{Configuration logic}
+
+The configuration logic selects either TX, CTS, or `off' depending on the mode
+of operation (section \ref{cfg}). The polarity of the TX signal depends
+on whether we operate in IR-UART or IrDA mode (section \ref{modesum}.
+Finally, if the configuration inputs are in their reset state, the mode is
+determined by bq.GPIO (section \ref{reset}).
+
+With the assumption that inputs default to ``0'' after reset,%
+\footnote{Most CPU pins default to ``0'' but some default to ``1''.
+ If using a GPIO that defaults to ``1'', the respective signal
+ has to be inverted by the configuration logic.
+ However, we will probably use signals from a GPIO expander
+ \cite{Neo900-iox}, which may default to high impedance after reset.
+ In this case, a suitable pull resistor is needed.}
+we can accomplish all this with the following circuit:
+
+\begin{center}
+\includegraphics[scale=0.9,]{logic.pdf}
+\end{center}
+
+The table below shows how the various modes are selected:
+
+\begin{tab}
+\begin{tabular}{l|cccc|c|l}
+ System state & \multicolumn{3}{c}{IR\_TX\_$\,...$} & bq.GPIO
+ & IR\_TX\_LED & Mode \\
+ & A & B & INV & & & \\
+ \hline
+ \rule{0pt}{12pt}\ignorespaces
+ Reset & 0 & 0 & 0 & 0 & 0 & Off or UART \\
+ & 0 & 0 & 0 & 1 & $\neg$TX & IR-UART \\
+ \hline
+ \rule{0pt}{12pt}\ignorespaces
+ Configured & 1 & 0 & 0 & X & 0 & Off or UART \\
+ & 1 & 1 & 0 & X & CTS & CIR \\
+ & 0 & 1 & 0 & X & $\neg$TX & IR-UART \\
+ & 0 & 1 & 1 & X & TX & IrDA \\
+\end{tabular}
+\end{tab}%
+%
+Since the circuit is too complicated to be implemented efficiently
+with discrete logic, we use a
+Silego SLG46531 mixed-signal array \cite{SLG46531}. This is the
+same chip also used for power selection in the Neo900 SIM switch
+\cite{Neo900-SIMSW}.
+
+% -----------------------------------------------------------------------------
+
\section{Overload protection}
\label{overload}
@@ -736,6 +788,13 @@ R6 pulls {\bf C} to ground in this case.
R7 ensures that CPU and Hackerbus can override the IR receiver,
especially when disabled or not illuminated.
+% -----------------------------------------------------------------------------
+
+\clearpage
+\begin{thebibliography}{8}
+\input ir.bbl
+\end{thebibliography}
+
\end{document}
% Jul 09 16:47:10 <DocScrutinizer05> re any multiplexing: I expect the whole IR section to get powered down by asserting a GPIO pin to a non-POR-default state, so the IR is active by default after power on reset. By connecting the whole IR via some series resistors to the UART, I expect anything on hackerbus to be able to override what comes from IR, particularly when IR is powered down
diff --git a/ir/logic.fig b/ir/logic.fig
index 3a6c5af..fa933e1 100644
--- a/ir/logic.fig
+++ b/ir/logic.fig
@@ -7,135 +7,86 @@ A4
Single
-2
1200 2
-5 1 0 2 0 7 50 -1 -1 0.000 0 1 0 0 7200.000 9405.000 7200 9630 7425 9405 7200 9180
-5 1 0 2 0 7 50 -1 -1 0.000 0 1 0 0 8415.000 9270.000 8415 9495 8640 9270 8415 9045
-5 1 0 2 0 7 50 -1 -1 0.000 0 1 0 0 9540.000 10035.000 9540 10260 9765 10035 9540 9810
-5 1 0 2 0 7 50 -1 -1 0.000 1 1 0 0 10113.750 9630.000 10350 9855 10440 9630 10350 9405
-5 1 0 2 0 7 50 -1 -1 0.000 1 0 0 0 10396.185 9960.395 10350 9405 10620 9450 10845 9630
-5 1 0 2 0 7 50 -1 -1 0.000 1 1 0 0 10396.185 9299.605 10350 9855 10620 9810 10845 9630
-5 1 0 2 0 7 50 -1 -1 0.000 0 1 0 0 7200.000 6300.000 7200 6525 7425 6300 7200 6075
-5 1 0 2 0 7 50 -1 -1 0.000 0 1 0 0 8415.000 6165.000 8415 6390 8640 6165 8415 5940
-5 1 0 2 0 7 50 -1 -1 0.000 0 1 0 0 9540.000 6930.000 9540 7155 9765 6930 9540 6705
-5 1 0 2 0 7 50 -1 -1 0.000 1 1 0 0 10113.750 6525.000 10350 6750 10440 6525 10350 6300
-5 1 0 2 0 7 50 -1 -1 0.000 1 0 0 0 10396.185 6855.395 10350 6300 10620 6345 10845 6525
-5 1 0 2 0 7 50 -1 -1 0.000 1 1 0 0 10396.185 6194.605 10350 6750 10620 6705 10845 6525
-1 3 0 2 0 7 50 -1 -1 0.000 1 0.0000 9180 9900 45 45 9180 9900 9180 9945
-1 3 0 2 0 7 50 -1 -1 0.000 1 0.0000 8055 6030 45 45 8055 6030 8055 6075
-2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
- 6570 3825 8280 3825
-2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
- 7875 3600 7875 4815
+5 1 0 2 0 7 50 -1 -1 0.000 1 0 0 0 8797.500 3060.000 9135 2880 9180 3060 9135 3240
+6 6645 2279 7036 2670
+5 1 0 2 0 7 60 -1 18 0.000 1 0 0 0 6840.000 2475.000 6840 2295 7020 2475 6840 2655
+2 1 0 2 0 7 60 -1 18 0.000 0 1 -1 0 0 4
+ 6840 2655 6660 2655 6660 2295 6840 2295
+-6
+6 7500 3044 7891 3435
+5 1 0 2 0 7 60 -1 18 0.000 1 0 0 0 7695.000 3240.000 7695 3060 7875 3240 7695 3420
+2 1 0 2 0 7 60 -1 18 0.000 0 1 -1 0 0 4
+ 7695 3420 7515 3420 7515 3060 7695 3060
+-6
+6 8280 2925 8775 3375
+5 1 0 2 0 7 55 -1 20 0.000 1 0 0 0 7987.500 3150.000 8325 2970 8370 3150 8325 3330
+5 1 0 2 0 7 60 -1 18 0.000 1 1 0 0 8339.318 2816.591 8325 3330 8550 3285 8730 3150
+5 1 0 2 0 7 60 -1 18 0.000 1 0 0 0 8339.318 3483.409 8325 2970 8550 3015 8730 3150
+2 3 0 0 0 7 65 -1 18 0.000 0 0 -1 0 0 4
+ 8325 3330 8325 2970 8730 3150 8325 3330
+-6
+6 9180 2835 9675 3285
+5 1 0 2 0 7 55 -1 20 0.000 1 0 0 0 8887.500 3060.000 9225 2880 9270 3060 9225 3240
+5 1 0 2 0 7 60 -1 18 0.000 1 1 0 0 9239.318 2726.591 9225 3240 9450 3195 9630 3060
+5 1 0 2 0 7 60 -1 18 0.000 1 0 0 0 9239.318 3393.409 9225 2880 9450 2925 9630 3060
+2 3 0 0 0 7 65 -1 18 0.000 0 0 -1 0 0 4
+ 9225 3240 9225 2880 9630 3060 9225 3240
+-6
+6 5655 2369 6046 2760
+5 1 0 2 0 7 60 -1 18 0.000 1 0 0 0 5850.000 2565.000 5850 2385 6030 2565 5850 2745
+2 1 0 2 0 7 60 -1 18 0.000 0 1 -1 0 0 4
+ 5850 2745 5670 2745 5670 2385 5850 2385
+-6
+6 3105 2925 5175 3690
+1 4 0 2 0 7 50 -1 -1 0.000 1 0.0000 5085 3150 45 45 5130 3150 5040 3150
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
+ 3915 3645 3825 3645 3825 2970 3915 2970
+2 3 0 2 0 7 60 -1 18 0.000 0 0 -1 0 0 4
+ 4770 3285 4770 2970 5040 3150 4770 3285
2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
- 6570 4230 8280 4230
+ 4320 3150 4770 3150
+4 2 0 50 -1 22 12 0.0000 4 135 330 4275 3555 CTS\001
+4 2 0 50 -1 18 12 0.0000 4 150 630 3735 3420 UART3\001
+4 2 0 50 -1 22 12 0.0000 4 135 210 4275 3195 TX\001
+-6
+1 4 0 2 0 7 50 -1 -1 0.000 1 0.0000 6615 2385 45 45 6660 2385 6570 2385
2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
- 5850 9990 7425 9990
+ 6300 1800 6300 3105
2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
- 5850 10350 7425 10350
-2 3 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
- 7425 10485 7425 9855 7830 9990 7830 10350 7425 10485
+ 6030 2565 6660 2565
2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
- 7650 9945 7650 8730
+ 6435 3330 7515 3330
+2 3 0 2 0 7 60 -1 18 0.000 0 0 -1 0 0 5
+ 6075 3645 6075 3015 6435 3150 6435 3510 6075 3645
2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
- 7200 9180 6885 9180 6885 9630 7200 9630
+ 5805 1575 5805 1485 9495 1485 9495 1575
2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
- 6885 9270 5850 9270
+ 6570 2385 6300 2385
2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 3
- 6525 10350 6525 9540 6885 9540
-2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
- 8415 9045 8100 9045 8100 9495 8415 9495
-2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
- 7425 9405 8100 9405
+ 7290 1800 7290 3150 7515 3150
2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
- 7830 10170 9225 10170
+ 7875 3240 8370 3240
2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
- 9540 9810 9225 9810 9225 10260 9540 10260
-2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 3
- 9135 9900 9000 9900 9000 8730
-2 1 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 4
- 8640 9270 10125 9270 10125 9495 10395 9495
-2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
- 9765 10035 10125 10035 10125 9765 10395 9765
-2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
- 10845 9630 11475 9630
-2 2 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
- 7290 9720 9900 9720 9900 10575 7290 10575 7290 9720
-2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
- 8100 9135 7650 9135
+ 7020 2475 8100 2475 8100 3060 8370 3060
2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
- 5850 6885 7425 6885
+ 8730 3150 9270 3150
2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
- 5850 7245 7425 7245
-2 3 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
- 7425 7380 7425 6750 7830 6885 7830 7245 7425 7380
-2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
- 7650 6840 7650 5625
-2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
- 7200 6075 6885 6075 6885 6525 7200 6525
-2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
- 6885 6165 5850 6165
+ 9630 3060 10035 3060
2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 3
- 6525 6885 6525 6435 6885 6435
-2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
- 8415 5940 8100 5940 8100 6390 8415 6390
-2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
- 7425 6300 8100 6300
+ 8910 1800 8910 2970 9270 2970
2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
- 7830 7065 9225 7065
-2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
- 9540 6705 9225 6705 9225 7155 9540 7155
+ 4320 2475 5670 2475
2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 3
- 9225 6795 9000 6795 9000 5625
-2 1 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 4
- 8640 6165 10125 6165 10125 6390 10395 6390
-2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
- 9765 6930 10125 6930 10125 6660 10395 6660
-2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
- 10845 6525 11475 6525
-2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
- 8010 6030 7650 6030
-4 1 0 50 -1 22 12 0.0000 4 180 645 7425 3780 bq.GPIO\001
-4 1 0 50 -1 22 12 0.0000 4 135 165 8100 3780 IR\001
-4 1 0 50 -1 22 12 0.0000 4 135 120 6975 3780 B\001
-4 1 0 50 -1 22 12 0.0000 4 135 120 6750 3780 A\001
-4 1 0 50 -1 22 12 0.0000 4 135 90 6975 4005 0\001
-4 1 0 50 -1 22 12 0.0000 4 135 90 6750 4005 0\001
-4 1 0 50 -1 22 12 0.0000 4 135 90 6750 4185 0\001
-4 1 0 50 -1 22 12 0.0000 4 135 90 6975 4185 0\001
-4 1 0 50 -1 22 12 0.0000 4 135 90 7425 4005 0\001
-4 1 0 50 -1 22 12 0.0000 4 135 90 7425 4185 1\001
-4 1 0 50 -1 22 12 0.0000 4 135 90 8100 4005 0\001
-4 1 0 50 -1 22 12 0.0000 4 135 210 8100 4185 TX\001
-4 0 0 50 -1 22 12 0.0000 4 180 900 5625 4590 Configured\001
-4 0 0 50 -1 22 12 0.0000 4 135 450 5625 4095 Reset\001
-4 0 0 50 -1 22 12 0.0000 4 180 3945 5625 5175 Assuming A, B reset to 0/L and are released to 0/L\001
-4 1 0 50 -1 22 12 0.0000 4 135 105 7425 4410 X\001
-4 1 0 50 -1 22 12 0.0000 4 135 105 7425 4590 X\001
-4 1 0 50 -1 22 12 0.0000 4 135 105 7425 4770 X\001
-4 1 0 50 -1 22 12 0.0000 4 135 90 6975 4410 0\001
-4 1 0 50 -1 22 12 0.0000 4 135 90 6750 4410 1\001
-4 1 0 50 -1 22 12 0.0000 4 135 90 8100 4410 0\001
-4 1 0 50 -1 22 12 0.0000 4 135 90 6750 4590 1\001
-4 1 0 50 -1 22 12 0.0000 4 135 90 6975 4590 1\001
-4 1 0 50 -1 22 12 0.0000 4 135 210 8100 4770 TX\001
-4 1 0 50 -1 22 12 0.0000 4 135 330 8100 4590 CTS\001
-4 1 0 50 -1 22 12 0.0000 4 135 90 6975 4770 1\001
-4 1 0 50 -1 22 12 0.0000 4 135 90 6750 4770 0\001
-4 2 0 50 -1 22 12 0.0000 4 180 645 5805 9315 bq.GPIO\001
-4 0 0 50 -1 22 8 0.0000 4 90 60 7470 10395 1\001
-4 0 0 50 -1 22 12 0.0000 4 135 165 11520 9675 IR\001
-4 1 0 50 -1 18 12 0.0000 4 150 255 7650 8685 nA\001
-4 1 0 50 -1 18 12 0.0000 4 150 255 9000 8685 nB\001
-4 1 0 50 -1 22 12 0.0000 4 135 1005 8550 10800 74AUP2G157\001
-4 0 0 50 -1 22 8 0.0000 4 90 60 7470 10035 0\001
-4 2 0 50 -1 22 12 0.0000 4 135 330 5805 10035 CTS\001
-4 2 0 50 -1 22 12 0.0000 4 135 210 5805 10395 TX\001
-4 2 0 50 -1 22 12 0.0000 4 135 330 5805 7290 CTS\001
-4 2 0 50 -1 22 12 0.0000 4 135 210 5805 6930 TX\001
-4 2 0 50 -1 22 12 0.0000 4 180 645 5805 6210 bq.GPIO\001
-4 0 0 50 -1 22 8 0.0000 4 90 60 7470 6930 0\001
-4 0 0 50 -1 22 8 0.0000 4 90 60 7470 7290 1\001
-4 0 0 50 -1 22 12 0.0000 4 135 165 11520 6570 IR\001
-4 1 0 50 -1 22 12 0.0000 4 135 1110 7605 7605 NC7SZ157L6X\001
-4 1 0 50 -1 18 12 0.0000 4 150 135 7650 5580 A\001
-4 1 0 50 -1 18 12 0.0000 4 150 135 9000 5580 B\001
-4 0 0 50 -1 22 12 0.0000 4 180 4185 5625 8325 Assuming nA, nB reset to 1/H and are released to 1/H\001
+ 5445 3150 5445 2655 5670 2655
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 5130 3150 6075 3150
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 6075 3510 4320 3510
+4 0 0 50 -1 22 8 0.0000 4 90 60 6120 3195 0\001
+4 0 0 50 -1 22 8 0.0000 4 90 60 6120 3555 1\001
+4 1 0 50 -1 18 12 0.0000 4 195 795 6300 1755 IR_TX_A\001
+4 1 0 50 -1 18 12 0.0000 4 195 795 7290 1755 IR_TX_B\001
+4 0 0 50 -1 18 12 0.0000 4 195 1050 10080 3105 IR_TX_LED\001
+4 1 0 50 -1 18 12 0.0000 4 195 990 8910 1755 IR_TX_INV\001
+4 1 0 50 -1 18 12 0.0000 4 150 600 7650 1395 GPIOs\001
+4 2 0 50 -1 22 12 0.0000 4 180 645 4275 2520 bq.GPIO\001