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authorWerner Almesberger <werner@almesberger.net>2015-01-05 19:07:16 (GMT)
committerWerner Almesberger <werner@almesberger.net>2015-01-05 19:07:16 (GMT)
commitb9c998eee87ab561d9a668c559c02594967db089 (patch)
tree7087e36a0d5fa8f47a1343c0373b9a2fa65740eb /nfc
parent4ea45b9e3df062ed17e1a4a88d75cd886f5c4cc9 (diff)
downloadmisc-b9c998eee87ab561d9a668c559c02594967db089.zip
misc-b9c998eee87ab561d9a668c559c02594967db089.tar.gz
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nfc/: Neo900 NFC architecture (draft, focus on evaluation)
Diffstat (limited to 'nfc')
-rw-r--r--nfc/Makefile82
-rw-r--r--nfc/card.fig35
-rw-r--r--nfc/comm.fig220
-rw-r--r--nfc/kl26-32.fig236
-rw-r--r--nfc/nfc.bib267
-rw-r--r--nfc/nfc.tex2445
-rw-r--r--nfc/pn-local.fig30
-rw-r--r--nfc/pn-shared.fig29
-rw-r--r--nfc/prefix.fig197
-rw-r--r--nfc/simseq.fig51
-rwxr-xr-xnfc/sortbib.pl48
-rw-r--r--nfc/stack.fig127
-rw-r--r--nfc/swp-cmp.fig70
-rw-r--r--nfc/swp-t.fig167
-rw-r--r--nfc/swp.fig38
-rw-r--r--nfc/sys.fig90
-rw-r--r--nfc/trf-comb.fig115
-rw-r--r--nfc/trf-dm-sysclk.fig76
-rw-r--r--nfc/trf-dm1-rx.fig71
-rw-r--r--nfc/trf-kl26.fig111
-rw-r--r--nfc/trf-sdm.fig74
-rw-r--r--nfc/trf-stack.fig84
-rw-r--r--nfc/trf-std.fig82
23 files changed, 4745 insertions, 0 deletions
diff --git a/nfc/Makefile b/nfc/Makefile
new file mode 100644
index 0000000..2ab4076
--- /dev/null
+++ b/nfc/Makefile
@@ -0,0 +1,82 @@
+FIGS = card stack sys prefix swp swp-t swp-cmp simseq \
+ pn-shared pn-local \
+ trf-stack trf-std trf-sdm trf-dm-sysclk trf-dm1-rx trf-comb trf-kl26 \
+ kl26-32
+
+FIGS_GEN = comm-rw-rdr comm-rw-card comm-ce-rdr comm-ce-card \
+ comm-p2p-init comm-p2p-tact comm-p2p-tpas
+
+TMP_SUFFIXES = aux bbl glg glo gls glsdefs ist log out
+
+FILT = ../../misc-pub/block/figfilt.pl
+filt = perl $(FILT) $(1) $< >$@ || { rm -f $@; exit 1; }
+
+.PHONY: all clean spotless
+.SUFFIXES: .fig .pdf
+
+NAME = nfc
+
+all: $(NAME).tex $(FIGS:%=%.pdf) $(FIGS_GEN:%=%.pdf) $(NAME).bbl
+ pdflatex $(NAME)
+ makeglossaries $(NAME)
+ pdflatex $(NAME)
+
+$(NAME).bbl: $(NAME).tex $(NAME).bib sortbib.pl
+ ./sortbib.pl $(NAME).tex $(NAME).bib >$@ || \
+ { rm -f "$@"; exit 1; }
+
+.fig.pdf:
+ fig2dev -L pdf $< $@
+
+# Layer
+# 10 Reader (L)
+# 15-17 Load modulation (R->L)
+# 20-22 Cards (R)
+# 25 Modulation R->L
+# 30 Wave R->L
+# 35 Modulation L->R
+# 40 Wave L->R
+# 50 Phone L
+# 60 Phone R
+# 65 "Target" (phone R)
+# 70 Power, data (L->R)
+# 75 Field, data (L->R)
+# 80 Field, data (R->L)
+# 85 Field (L->R)
+# 90 Power (L->R)
+# 100 Battery (phone R)
+# 105 Battey solid (phone R)
+# 110 Battey optional (phone R)
+# 120-122 Secure Element
+# 125 Communication to SE
+# 130 Communication from SE
+
+COMM_DEP = comm.fig $(FILT) Makefile
+comm-rw-rdr.fig: $(COMM_DEP)
+ $(call filt, 10:20-22:35:40:70)
+
+comm-rw-card.fig: $(COMM_DEP)
+ $(call filt, 10:15-17:20-22:40:90)
+
+comm-ce-rdr.fig: $(COMM_DEP)
+ $(call filt, 10:60:35:40:70:100:110:120:125:140)
+
+comm-ce-card.fig: $(COMM_DEP)
+ $(call filt, 10:15-17:60:40:90:100:110:120:130:140)
+
+comm-p2p-init.fig: $(COMM_DEP)
+ $(call filt, 50:60-65:35:40:75:100:105)
+
+comm-p2p-tact.fig: $(COMM_DEP)
+ $(call filt, 50:60-65:25:30:100:105)
+
+comm-p2p-tpas.fig: $(COMM_DEP)
+ $(call filt, 15-17:50:60-65:40:85:100:105)
+
+clean:
+ rm -f $(FIGS:%=%.pdf)
+ rm -f $(FIGS_GEN:%=%.pdf) $(FIGS_GEN:%=%.fig)
+ rm -f $(TMP_SUFFIXES:%=$(NAME).%)
+
+spotless: clean
+ rm -f $(NAME).pdf
diff --git a/nfc/card.fig b/nfc/card.fig
new file mode 100644
index 0000000..8607f30
--- /dev/null
+++ b/nfc/card.fig
@@ -0,0 +1,35 @@
+#FIG 3.2 Produced by xfig version 3.2.5c
+Landscape
+Center
+Metric
+A4
+100.00
+Single
+-2
+1200 2
+2 2 0 2 0 7 50 -1 20 0.000 0 0 -1 0 0 5
+ 5400 6075 5850 6075 5850 6750 5400 6750 5400 6075
+2 2 0 2 0 7 50 -1 20 0.000 0 0 -1 0 0 5
+ 6075 6075 6975 6075 6975 6300 6075 6300 6075 6075
+2 2 0 2 0 7 50 -1 20 0.000 0 0 -1 0 0 5
+ 6075 6300 6975 6300 6975 6525 6075 6525 6075 6300
+2 2 0 2 0 7 50 -1 20 0.000 0 0 -1 0 0 5
+ 6075 6525 6975 6525 6975 6750 6075 6750 6075 6525
+2 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 0 0 2
+ 5850 6210 6075 6210
+2 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 0 0 2
+ 5850 6435 6075 6435
+2 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 0 0 2
+ 5850 6660 6075 6660
+2 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 1 1 2
+ 1 1 2.00 60.00 60.00
+ 1 1 2.00 60.00 60.00
+ 5400 6435 4500 6435
+2 4 0 2 0 7 55 -1 18 0.000 0 0 8 0 0 5
+ 7200 6975 5175 6975 5175 5850 7200 5850 7200 6975
+4 1 0 45 -1 22 12 0.0000 4 135 225 5625 6480 RF\001
+4 1 0 45 -1 22 12 0.0000 4 135 285 6525 6255 UID\001
+4 1 0 45 -1 22 12 0.0000 4 180 630 6525 6480 Memory\001
+4 1 0 45 -1 22 12 0.0000 4 135 210 6525 6705 SE\001
+4 1 0 45 -1 22 12 0.0000 4 135 1170 6165 5715 NFC/RFID card\001
+4 2 0 45 -1 22 12 0.0000 4 135 555 4455 6480 Reader\001
diff --git a/nfc/comm.fig b/nfc/comm.fig
new file mode 100644
index 0000000..a1cbe3c
--- /dev/null
+++ b/nfc/comm.fig
@@ -0,0 +1,220 @@
+#FIG 3.2 Produced by xfig version 3.2.5c
+Landscape
+Center
+Metric
+A4
+100.00
+Single
+-2
+1200 2
+0 32 #d0d0d0
+5 1 0 3 0 7 15 -1 -1 0.000 0 1 0 0 6750.000 5175.000 6210 4950 6165 5175 6210 5400
+5 1 0 3 0 7 15 -1 -1 0.000 0 1 0 0 6975.000 5175.000 6795 5040 6750 5175 6795 5310
+# L4
+5 1 0 3 32 7 25 -1 -1 0.000 0 1 0 0 7110.000 5175.000 6435 4815 6345 5175 6435 5535
+# L7
+5 1 0 3 32 7 25 -1 -1 0.000 0 1 0 0 7211.250 5175.000 5895 4680 5805 5175 5895 5670
+# L8
+5 1 0 3 0 7 30 -1 -1 0.000 0 1 0 0 7290.000 5175.000 5715 4635 5625 5175 5715 5715
+# L7
+5 1 0 3 0 7 30 -1 -1 0.000 0 1 0 0 7211.250 5175.000 5895 4680 5805 5175 5895 5670
+# L6
+5 1 0 3 0 7 30 -1 -1 0.000 0 1 0 0 7155.000 5175.000 6075 4725 5985 5175 6075 5625
+# L5
+5 1 0 3 0 7 30 -1 -1 0.000 0 1 0 0 7121.250 5175.000 6255 4770 6165 5175 6255 5580
+# L4
+5 1 0 3 0 7 30 -1 -1 0.000 0 1 0 0 7110.000 5175.000 6435 4815 6345 5175 6435 5535
+# L3
+5 1 0 3 0 7 30 -1 -1 0.000 0 1 0 0 7121.250 5175.000 6615 4860 6525 5175 6615 5490
+# L2
+5 1 0 3 0 7 30 -1 -1 0.000 0 1 0 0 7155.000 5175.000 6795 4905 6705 5175 6795 5445
+# L1
+5 1 0 3 0 7 30 -1 -1 0.000 0 1 0 0 7211.250 5175.000 6975 4950 6885 5175 6975 5400
+# R3
+5 1 0 3 32 7 35 -1 -1 0.000 0 0 0 0 5478.750 5175.000 5985 4860 6075 5175 5985 5490
+# R6
+5 1 0 3 32 7 35 -1 -1 0.000 0 0 0 0 5445.000 5175.000 6525 4725 6615 5175 6525 5625
+# R1
+5 1 0 3 0 7 40 -1 -1 0.000 0 0 0 0 5388.750 5175.000 5625 4950 5715 5175 5625 5400
+# R2
+5 1 0 3 0 7 40 -1 -1 0.000 0 0 0 0 5445.000 5175.000 5805 4905 5895 5175 5805 5445
+# R3
+5 1 0 3 0 7 40 -1 -1 0.000 0 0 0 0 5478.750 5175.000 5985 4860 6075 5175 5985 5490
+# R4
+5 1 0 3 0 7 40 -1 -1 0.000 0 0 0 0 5490.000 5175.000 6165 4815 6255 5175 6165 5535
+# R5
+5 1 0 3 0 7 40 -1 -1 0.000 0 0 0 0 5478.750 5175.000 6345 4770 6435 5175 6345 5580
+# R6
+5 1 0 3 0 7 40 -1 -1 0.000 0 0 0 0 5445.000 5175.000 6525 4725 6615 5175 6525 5625
+# R7
+5 1 0 3 0 7 40 -1 -1 0.000 0 0 0 0 5388.750 5175.000 6705 4680 6795 5175 6705 5670
+# R8
+5 1 0 3 0 7 40 -1 -1 0.000 0 0 0 0 5310.000 5175.000 6885 4635 6975 5175 6885 5715
+5 1 0 2 0 7 10 -1 -1 0.000 1 0 0 0 4275.000 5265.000 4185 5265 4275 5175 4365 5265
+# SmartA
+6 4590 4920 5295 5400
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4650 5250 4650 5385
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 5235 5250 5235 5385
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 5145 5250 5145 5385
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 5190 5250 5190 5385
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4695 5250 4695 5385
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4740 5250 4740 5385
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4785 5250 4785 5385
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4650 5340 5235 5340
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4650 5295 5235 5295
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 5100 5250 5100 5385
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 5055 5340 5055 5250
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 5010 5250 5010 5385
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4965 5250 4965 5385
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4920 5250 4920 5385
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4875 5250 4875 5385
+2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4830 5250 4830 5385
+2 2 0 2 0 7 50 -1 18 0.000 0 0 -1 0 0 5
+ 4695 4980 5190 4980 5190 5205 4695 5205 4695 4980
+2 4 0 2 0 7 50 -1 -1 0.000 0 0 4 0 0 5
+ 5280 5385 4605 5385 4605 4935 5280 4935 5280 5385
+2 4 0 2 0 7 50 -1 -1 0.000 0 0 4 0 0 5
+ 5280 5250 4605 5250 4605 4935 5280 4935 5280 5250
+-6
+# SmartB
+6 7200 4920 7905 5400
+2 1 0 1 0 7 60 -1 -1 0.000 0 0 -1 0 0 2
+ 7260 5250 7260 5385
+2 1 0 1 0 7 60 -1 -1 0.000 0 0 -1 0 0 2
+ 7845 5250 7845 5385
+2 1 0 1 0 7 60 -1 -1 0.000 0 0 -1 0 0 2
+ 7755 5250 7755 5385
+2 1 0 1 0 7 60 -1 -1 0.000 0 0 -1 0 0 2
+ 7800 5250 7800 5385
+2 1 0 1 0 7 60 -1 -1 0.000 0 0 -1 0 0 2
+ 7305 5250 7305 5385
+2 1 0 1 0 7 60 -1 -1 0.000 0 0 -1 0 0 2
+ 7350 5250 7350 5385
+2 1 0 1 0 7 60 -1 -1 0.000 0 0 -1 0 0 2
+ 7395 5250 7395 5385
+2 1 0 1 0 7 60 -1 -1 0.000 0 0 -1 0 0 2
+ 7260 5340 7845 5340
+2 1 0 1 0 7 60 -1 -1 0.000 0 0 -1 0 0 2
+ 7260 5295 7845 5295
+2 1 0 1 0 7 60 -1 -1 0.000 0 0 -1 0 0 2
+ 7710 5250 7710 5385
+2 1 0 1 0 7 60 -1 -1 0.000 0 0 -1 0 0 2
+ 7665 5340 7665 5250
+2 1 0 1 0 7 60 -1 -1 0.000 0 0 -1 0 0 2
+ 7620 5250 7620 5385
+2 1 0 1 0 7 60 -1 -1 0.000 0 0 -1 0 0 2
+ 7575 5250 7575 5385
+2 1 0 1 0 7 60 -1 -1 0.000 0 0 -1 0 0 2
+ 7530 5250 7530 5385
+2 1 0 1 0 7 60 -1 -1 0.000 0 0 -1 0 0 2
+ 7485 5250 7485 5385
+2 1 0 1 0 7 60 -1 -1 0.000 0 0 -1 0 0 2
+ 7440 5250 7440 5385
+2 2 0 2 0 7 60 -1 18 0.000 0 0 -1 0 0 5
+ 7305 4980 7800 4980 7800 5205 7305 5205 7305 4980
+2 4 0 2 0 7 60 -1 -1 0.000 0 0 4 0 0 5
+ 7890 5385 7215 5385 7215 4935 7890 4935 7890 5385
+2 4 0 2 0 7 60 -1 -1 0.000 0 0 4 0 0 5
+ 7890 5250 7215 5250 7215 4935 7890 4935 7890 5250
+-6
+# Reader
+2 2 0 2 0 7 10 -1 -1 0.000 0 0 -1 0 0 5
+ 4500 4500 5400 4500 5400 5850 4500 5850 4500 4500
+# Card
+2 4 0 2 0 7 21 -1 20 0.000 0 0 5 0 0 5
+ 7920 4950 7200 4950 7200 5400 7920 5400 7920 4950
+2 2 0 0 32 7 17 -1 20 0.000 0 0 -1 0 0 5
+ 6750 5040 6840 5040 6840 5310 6750 5310 6750 5040
+2 2 0 0 32 7 17 -1 20 0.000 0 0 -1 0 0 5
+ 6210 4950 6300 4950 6300 5400 6210 5400 6210 4950
+2 1 0 2 0 7 35 -1 -1 0.000 0 0 -1 0 0 2
+ 6030 5535 6165 6075
+2 1 0 2 0 7 35 -1 -1 0.000 0 0 -1 0 0 2
+ 6480 5715 6345 6075
+2 1 0 2 0 7 40 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 60.00
+ 5625 4455 6975 4455
+2 1 0 2 0 7 15 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 60.00
+ 6975 6075 5625 6075
+2 1 0 2 0 7 15 -1 -1 0.000 0 0 -1 0 0 2
+ 6255 5625 6660 6300
+2 1 0 2 0 7 15 -1 -1 0.000 0 0 -1 0 0 2
+ 6750 5715 6750 6300
+2 1 0 2 0 7 25 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 60.00
+ 6975 6075 5625 6075
+2 1 0 2 0 7 25 -1 -1 0.000 0 0 -1 0 0 2
+ 5895 4635 6030 4410
+2 1 0 2 0 7 25 -1 -1 0.000 0 0 -1 0 0 2
+ 6390 4770 6210 4410
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 3
+ 4365 5130 4365 5040 4590 5040
+2 1 0 2 0 7 105 -1 -1 0.000 0 0 -1 0 0 3
+ 8280 5130 8280 5040 7875 5040
+2 1 0 2 0 7 105 -1 -1 0.000 0 0 -1 0 0 3
+ 8280 5220 8280 5310 7875 5310
+2 1 1 2 0 7 110 -1 -1 3.000 0 0 -1 0 0 3
+ 8280 5130 8280 5040 7875 5040
+2 1 1 2 0 7 110 -1 -1 3.000 0 0 -1 0 0 3
+ 8280 5220 8280 5310 7875 5310
+2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4230 5130 4500 5130
+2 1 0 3 0 7 100 -1 -1 0.000 0 0 -1 0 0 2
+ 8145 5130 8415 5130
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 3
+ 4365 5220 4365 5310 4590 5310
+2 2 0 1 0 7 50 -1 0 0.000 0 0 -1 0 0 5
+ 4275 5175 4455 5175 4455 5220 4275 5220 4275 5175
+2 2 0 1 0 7 100 -1 0 0.000 0 0 -1 0 0 5
+ 8190 5175 8370 5175 8370 5220 8190 5220 8190 5175
+2 1 0 2 0 7 10 -1 -1 0.000 0 1 -1 0 0 4
+ 4185 5265 4230 5400 4320 5400 4365 5265
+# Card
+2 4 0 2 0 7 22 -1 -1 0.000 0 0 5 0 0 5
+ 8010 5040 7290 5040 7290 5490 8010 5490 8010 5040
+2 1 1 2 0 7 130 -1 -1 2.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 60.00
+ 7695 5625 7695 5400
+2 1 1 2 0 7 125 -1 -1 2.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 60.00
+ 7695 5400 7695 5625
+2 3 1 2 0 7 120 -1 -1 1.500 0 0 -1 0 0 6
+ 7560 5760 7560 5670 7605 5625 7785 5625 7785 5760 7560 5760
+2 3 0 2 32 7 140 -1 -1 0.000 0 0 -1 0 0 6
+ 7560 5760 7560 5670 7605 5625 7785 5625 7785 5760 7560 5760
+3 2 0 2 0 7 10 -1 -1 0.000 0 0 0 3
+ 4275 5400 4320 5580 4500 5625
+ 0.000 -1.000 0.000
+# Reader
+4 1 0 10 -1 22 12 0.0000 4 135 555 4950 5220 Reader\001
+# Card
+4 1 0 20 -1 22 12 0.0000 4 180 585 7560 5265 Card(s)\001
+4 1 0 35 -1 22 12 0.0000 4 180 1785 6255 6300 Amplitude modulation\001
+4 1 0 90 -1 22 12 0.0000 4 135 480 6255 4410 Power\001
+4 1 0 15 -1 22 12 0.0000 4 135 360 6075 6030 Data\001
+4 1 0 15 -1 22 12 0.0000 4 135 1365 6750 6480 Load modulation\001
+4 1 0 70 -1 22 12 0.0000 4 165 915 6255 4410 Power, data\001
+4 1 0 75 -1 22 12 0.0000 4 165 825 6255 4410 Field, data\001
+4 1 0 25 -1 22 12 0.0000 4 165 825 6345 6030 Field, data\001
+4 1 0 85 -1 22 12 0.0000 4 135 390 6255 4410 Field\001
+4 1 0 25 -1 22 12 0.0000 4 180 1785 6120 4365 Amplitude modulation\001
+4 1 0 120 -1 22 12 0.0000 4 135 1215 7695 5940 Secure element\001
+4 1 0 50 -1 22 12 0.0000 4 135 615 4950 4725 Initiator\001
+4 1 0 65 -1 22 12 0.0000 4 180 510 7560 4725 Target\001
diff --git a/nfc/kl26-32.fig b/nfc/kl26-32.fig
new file mode 100644
index 0000000..f4166e1
--- /dev/null
+++ b/nfc/kl26-32.fig
@@ -0,0 +1,236 @@
+#FIG 3.2 Produced by xfig version 3.2.5c
+Landscape
+Center
+Metric
+A4
+100.00
+Single
+-2
+1200 2
+6 7875 1530 10125 2700
+4 0 0 50 -1 22 12 0.0000 4 165 1200 7875 2655 IxC = I2Cx_SCL\001
+4 0 0 50 -1 22 12 0.0000 4 165 1215 7875 2430 IxD = I2Cx_SDA\001
+4 0 0 50 -1 22 12 0.0000 4 165 1335 7875 2115 SxS = SPIx_PCS0\001
+4 0 0 50 -1 22 12 0.0000 4 165 1275 7875 1890 SxC = SPIx_SCK\001
+4 0 0 50 -1 22 12 0.0000 4 165 2235 7875 1665 SxM = SPIx_MOSI/SPIx_MISO\001
+-6
+1 3 0 2 0 7 50 -1 -1 0.000 1 0.0000 4455 4005 64 64 4455 4005 4500 4050
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4050 5175 4275 5175
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4050 4950 4275 4950
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4050 4725 4275 4725
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4050 5400 4275 5400
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4050 5625 4275 5625
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4050 5850 4275 5850
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4050 4500 4275 4500
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4050 4275 4275 4275
+2 2 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+ 4275 3825 6750 3825 6750 6300 4275 6300 4275 3825
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 6750 4275 6975 4275
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 6750 4500 6975 4500
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 6750 4725 6975 4725
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 6750 4950 6975 4950
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 6750 5175 6975 5175
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 6750 5400 6975 5400
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 6750 5625 6975 5625
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 6750 5850 6975 5850
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4725 3600 4725 3825
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4950 3600 4950 3825
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 5175 3600 5175 3825
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 5400 3600 5400 3825
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 5625 3600 5625 3825
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 5850 3600 5850 3825
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 6075 3600 6075 3825
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 6300 3600 6300 3825
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 6300 6300 6300 6525
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 6075 6300 6075 6525
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 5850 6300 5850 6525
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+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
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+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+ 1 1 2.00 60.00 90.00
+ 6300 3555 6300 1800 2925 1800
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+ 1 1 2.00 60.00 90.00
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+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
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+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
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+ 2925 7200 5175 7200 5175 6570
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+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 4
+ 1 1 2.00 60.00 90.00
+ 2925 8100 7425 8100 7425 5850 7020 5850
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
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+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 1 2
+ 1 1 2.00 60.00 90.00
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+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 1 2
+ 1 1 2.00 60.00 90.00
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+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
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+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
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+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 4
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+ 4950 3555 4950 2925 7875 2925 7875 7425
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 5
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+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
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+2 2 0 0 0 7 55 -1 15 0.000 0 0 7 0 0 5
+ 6750 5085 6750 5265 6705 5265 6705 5085 6750 5085
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 4950 8775 4950 6975
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 1 2
+ 1 1 2.00 60.00 90.00
+ 1 1 2.00 60.00 90.00
+ 5625 8775 5625 7650
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
+ 4860 8775 4860 8865 5715 8865 5715 8775
+2 2 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+ 7785 7425 7965 7425 7965 7875 7785 7875 7785 7425
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 7875 7875 7875 8775
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+ 1 1 2.00 60.00 90.00
+ 5850 6615 5850 7875 2925 7875
+4 2 0 50 -1 22 12 0.0000 4 135 285 3960 5895 Pwr\001
+4 2 0 50 -1 22 12 0.0000 4 135 345 3960 4995 USB\001
+4 2 0 50 -1 22 12 1.5708 4 135 300 5445 3915 S1S\001
+4 2 0 50 -1 22 12 1.5708 4 135 315 5220 3915 S1C\001
+4 2 0 50 -1 22 12 1.5708 4 135 330 4995 3915 S1M\001
+4 2 0 50 -1 22 12 1.5708 4 135 330 5670 3915 S0M\001
+4 2 0 50 -1 22 12 1.5708 4 135 330 5895 3915 S0M\001
+4 2 0 50 -1 22 12 1.5708 4 135 315 6120 3915 S0C\001
+4 2 0 50 -1 22 12 1.5708 4 135 300 6345 3915 S0S\001
+4 2 0 50 -1 22 12 1.5708 4 135 330 4770 3915 S1M\001
+4 0 0 50 -1 22 12 0.0000 4 135 900 4635 4635 S1MISO/I1D\001
+4 0 0 50 -1 22 12 1.5708 4 165 1050 5670 6210 I1C/SWD_DIO\001
+4 0 0 50 -1 22 12 1.5708 4 135 705 5895 6210 I1D/nNMI\001
+4 0 0 50 -1 22 12 1.5708 4 165 810 4995 6210 SWD_CLK\001
+4 2 0 50 -1 22 12 0.0000 4 135 345 2835 4320 RXD\001
+4 2 0 50 -1 22 12 0.0000 4 135 345 3960 4770 USB\001
+4 2 0 50 -1 22 12 0.0000 4 135 285 3960 4545 Pwr\001
+4 2 0 50 -1 22 12 0.0000 4 135 285 3960 5220 Pwr\001
+4 2 0 50 -1 22 12 0.0000 4 135 285 3960 5445 Pwr\001
+4 2 0 50 -1 22 12 0.0000 4 135 285 3960 5670 Pwr\001
+4 2 0 50 -1 22 12 1.5708 4 135 285 6120 6615 Pwr\001
+4 2 0 50 -1 22 12 1.5708 4 135 285 6345 6615 Pwr\001
+4 2 0 50 -1 22 12 0.0000 4 165 765 2835 2745 TRX_CLK\001
+4 2 0 50 -1 22 12 0.0000 4 135 750 2835 2970 TXD/MOD\001
+4 2 0 50 -1 22 12 0.0000 4 135 405 2835 2520 MISO\001
+4 2 0 50 -1 22 12 0.0000 4 135 405 2835 2295 MOSI\001
+4 2 0 50 -1 22 12 0.0000 4 135 315 2835 1845 nSS\001
+4 2 0 50 -1 22 12 0.0000 4 135 450 2835 2070 SCLK\001
+4 1 0 50 -1 22 12 0.0000 4 135 1005 5490 4995 Kinetis KL26\001
+4 0 0 50 -1 22 12 1.5708 4 165 795 4770 6210 CMP0_IN4\001
+4 2 0 50 -1 18 8 0.0000 4 90 75 4185 6030 8\001
+4 0 0 50 -1 18 8 0.0000 4 90 150 6840 4185 24\001
+4 0 0 50 -1 18 8 0.0000 4 90 150 6390 3735 25\001
+4 0 0 50 -1 18 8 0.0000 4 90 150 6390 6480 16\001
+4 2 0 50 -1 18 8 0.0000 4 90 75 4635 6480 9\001
+4 2 0 50 -1 18 8 0.0000 4 90 150 4635 3735 32\001
+4 2 0 50 -1 18 8 0.0000 4 90 75 4185 4185 1\001
+4 2 0 50 -1 22 12 0.0000 4 135 255 6660 4545 I1D\001
+4 2 0 50 -1 22 12 0.0000 4 135 255 6660 4770 I1C\001
+4 2 0 50 -1 22 12 0.0000 4 135 255 6660 4995 I0D\001
+4 2 0 50 -1 22 12 0.0000 4 135 255 6660 5220 I0C\001
+4 0 0 50 -1 22 12 0.0000 4 135 345 8865 4995 SDA\001
+4 0 0 50 -1 22 12 0.0000 4 135 330 8865 5220 SCL\001
+4 2 0 50 -1 22 12 0.0000 4 135 645 6660 5445 nRESET\001
+4 0 0 50 -1 22 12 0.0000 4 165 1080 8865 5445 NFC_nRESET\001
+4 2 0 50 -1 22 12 0.0000 4 135 630 6660 5895 EXTAL0\001
+4 0 0 50 -1 18 8 0.0000 4 90 150 6840 6030 17\001
+4 1 0 50 -1 22 12 0.0000 4 165 645 6975 2880 SWP_S1\001
+4 1 0 50 -1 22 12 0.0000 4 135 420 6975 3105 SELF\001
+4 1 0 50 -1 22 12 4.7124 4 135 615 10080 5040 DM3730\001
+4 1 0 50 -1 22 12 1.5708 4 135 810 1890 4860 TRF7970A\001
+4 0 0 50 -1 22 12 0.0000 4 165 705 8865 4770 NFC_INT\001
+4 2 0 50 -1 22 12 0.0000 4 165 780 2835 8145 NFC_CLK\001
+4 1 0 50 -1 22 12 0.0000 4 135 375 5265 9090 SWD\001
+4 0 0 50 -1 22 12 0.0000 4 135 585 8055 7605 Rshunt\001
+4 0 0 50 -1 22 12 0.0000 4 135 270 8055 7830 150\001
+4 1 0 50 -1 22 12 0.0000 4 135 420 7875 9000 SWIO\001
+4 1 0 50 -1 22 12 0.0000 4 165 645 6750 8280 SWP_S2\001
+4 2 0 50 -1 22 12 0.0000 4 165 525 2835 7020 TX_EN\001
+4 2 0 50 -1 22 12 0.0000 4 135 285 2835 7245 IRQ\001
+4 2 0 50 -1 22 12 0.0000 4 135 540 2835 7470 Enable\001
+4 2 0 50 -1 22 12 0.0000 4 135 360 2835 7695 OOK\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 2835 7920 IO_1\001
diff --git a/nfc/nfc.bib b/nfc/nfc.bib
new file mode 100644
index 0000000..eaba9d3
--- /dev/null
+++ b/nfc/nfc.bib
@@ -0,0 +1,267 @@
+%----- Overviews --------------------------------------------------------------
+
+\bibitem{ISO14443}OpenPCD project.
+ {\em ISO14443},
+ \url{http://www.openpcd.org/ISO14443}
+
+\bibitem{MIFARE-Classic}OpenPCD project.
+ {\em Mifare Classic},
+ \url{http://www.openpcd.org/Mifare_Classic}
+
+\bibitem{Atmel2056B}Atmel Corporation.
+ {\em Requirements of ISO/IEC 14443 Type B Proximity Contactless
+ Identification Cards},
+ Rev. 2056B-RFID-11/05.
+ \url{http://www.atmel.com/images/doc2056.pdf}
+
+\bibitem{NFCtags}NXP Semiconductors.
+ {\em NFC Forum Type Tags},
+ White Paper V1.0, April 2009.
+ \url{http://members.nfc-forum.org/resources/white_papers/NXP_BV_Type_Tags_White_Paper-Apr_09.pdf}
+
+\bibitem{TI14443}Texas Instruments.
+ {\em ISO/IEC 14443 Overview},
+ \url{http://e2e.ti.com/cfs-file/__key/telligent-evolution-components-attachments/00-667-01-00-00-30-14-15/ISO14443-Overview_2D00_v5.ppt}
+
+\bibitem{LinuxNFC2011}Venancio, Lauro Ramos; Ortiz, Samuel.
+ {\em Linux NFC Subsystem},
+ October 2011.
+ \url{http://elinux.org/images/a/a9/Elce11_venancio_ortiz.pdf}
+
+\bibitem{}EVB Elektronik.
+ {\em Identification Selection Guide},
+ Version 3, March 2014.
+ \url{http://www.ebv.com/fileadmin/design_solutions/php/download.php?path=uploads%2Ftx_downloadarea%2FP-049-E-05-2013-v3_RFID_Selection_Guide_neu.pdf}
+% \url{http://www.adafruit.com/datasheets/rfid%20guide.pdf}
+
+%----- ISO NFC standards ------------------------------------------------------
+
+\bibitem{ISO14443-2}ISO/IEC JTC 1/SC 17/WG 8.
+ {\em Identification cards -- Contactless integrated circuit(s) cards
+ -- Proximity cards -- Part 2: Radio frequency power and signal interface},
+ ISO/IEC FDIS 14443-2:2009(E), July 2009.
+
+\bibitem{ISO14443-3}ISO/IEC JTC 1/SC 17/WG 8.
+ {\em Identification cards -- Contactless integrated circuit(s) cards --
+ Proximity cards -- Part 3: Initialization and anticollision},
+ November 2008.
+
+\bibitem{ISO14443-4}ISO/IEC JTC 1/SC 17/WG 8.
+ {\em Identification cards -- Contactless integrated circuit(s) cards --
+ Proximity cards -- Part 4: Transmission protocol},
+ March 2007.
+
+\bibitem{ISO15693-2}ISO/IEC.
+ {\em Identification cards -- Contactless integrated circuit(s) cards --
+ Vicinity cards -- Part 2: Radio frequency power and signal interface},
+ ISO/IEC FCD 15693-2, March 1999.
+
+\bibitem{ISO15693-3}ISO/IEC JTC 1/SC 17/WG 8.
+ {\em Identification cards -- Contactless integrated circuit(s) cards --
+ Vicinity cards -- Part 3: Anti-collision and transmission protocol},
+ ISO/IEC FCD 15693-3, March 2000.
+
+\bibitem{ISO18000-3}ISO/IEC 18000-3.
+ {\em Information technology -- Radio frequency identification for item
+ management -- Part 3: Parameters for air interface communications at
+ 13,56 MHz},
+ ISO/IEC 18000-3:2004(E), First edition, September 2004.
+
+%----- ECMA NFC standards -----------------------------------------------------
+
+\bibitem{NFCIP1}ECMA-340.
+ {\em Near Field Communication -- Interface and Protocol (NFCIP-1)},
+ 3rd edition, June 2013.
+ \url{http://www.ecma-international.org/publications/files/ECMA-ST/Ecma-340.pdf}
+
+\bibitem{NFCIP2}ECMA-352.
+ {\em Near Field Communication Interface and Protocol -- 2 (NFCIP-2)},
+ 1st edition, December 2003.
+ \url{http://www.ecma-international.org/publications/files/ECMA-ST/Ecma-352.pdf}
+
+%----- JIS NFC standards ------------------------------------------------------
+
+\bibitem{FeliCa}Japanese Standards Association.
+ {\em Specification of implementation for integrated circuit(s) cards --
+ Part 4: High Speed proximity cards},
+ JIS X 6319-4, July 2005.
+
+%----- ISO Card standards -----------------------------------------------------
+
+\bibitem{ISO7816-3}ISO/IEC 7816-3.
+ {\em Identification cards -- Integrated circuit cards -- Part 3:
+ Cards with contacts -- Electrical interface and transmission protocols},
+ ISO/IEC 7816-3:2006(E), Third edition, November 2006.
+
+%----- ETSI Card standards ----------------------------------------------------
+
+\bibitem{UICC}ETSI TS 102 221 V11.1.0 (2013-11).
+ {\em Smart Cards; UICC-Terminal interface;
+ Physical and logical characteristics (Release 11)},
+ \url{http://www.etsi.org/deliver/etsi_ts/102200_102299/102221/11.01.00_60/ts_102221v110100p.pdf}
+
+\bibitem{SWP}ETSI TS 102 613 V11.0.0 (2012-09).
+ {\em Smart Cards; UICC - Contactless Front-end (CLF) Interface;
+ Part 1: Physical and data link layer characteristics (Release 11)},
+ \url{http://www.etsi.org/deliver/etsi_ts/102600_102699/102613/11.00.00_60/ts_102613v110000p.pdf}
+
+%----- NFC Forum Specifications -----------------------------------------------
+
+\bibitem{NFCdigital}NFC Forum.
+ {\em NFC Digital Protocol},
+ DIGITAL 1.0, November 2010.
+
+\bibitem{NFCtag1}NFC Forum.
+ {\em Type 1 Tag Operation Specification},
+ T1TOP 1.1, April 2011.
+
+\bibitem{NFCtag2}NFC Forum.
+ {\em Type 2 Tag Operation Specification},
+ T2TOP 1.1, May 2011.
+
+\bibitem{NFCtag3}NFC Forum.
+ {\em Type 3 Tag Operation Specification},
+ T3TOP 1.1, June 2011.
+
+\bibitem{NFCtag4}NFC Forum.
+ {\em Type 4 Tag Operation Specification},
+ T4TOP 2.0, June 2011.
+
+%----- EMV (EMVCo) ------------------------------------------------------------
+
+\bibitem{EMV}EMVCo.
+ {\em EMV Contactless Specifications for Payment Systems --
+ Book D -- EMV Contactless Communication Protocol Specification},
+ Version 2.4, February 2014.
+ \url{http://www.emvco.com/download_agreement.aspx?id=954}
+
+%----- NFC chips --------------------------------------------------------------
+
+\bibitem{TRF7970A}Texas Instruments Incorporated.
+ {\em TRF7970A Multiprotocol Fully Integrated 13.56-MHz RFID and
+ Near Field Communication (NFC) Transceiver IC},
+ SLOS743K, April 2014.
+ \url{http://www.ti.com/lit/pdf/slos743}
+
+\bibitem{TRF-FW}Wyatt, Josh; Aslanidis, Kostas; Mayer-Zintel, Juergen.
+ {\em TRF7970A Firmware Design Hints},
+ Texas Instruments Incorporated, SLOA159, August 2011.
+ \url{http://www.ti.com/lit/pdf/sloa159}
+
+\bibitem{TRF-POWER-DOWN}Kozitsky, Alexander.
+ {\em Minimizing TRF79xx Current Use During PowerDown Mode},
+ Texas Instruments Incorporated, SLOA205, August 2014.
+ \url{http://www.ti.com/lit/pdf/sloa205}
+
+\bibitem{TRF-ANT}Schillinger, John.
+ {\em Antenna Matching for the TRF7960 RFID Reader},
+ Texas Instruments Incorporated, SLOA135A, September 2013.
+ \url{http://www.ti.com/lit/pdf/sloa135a}
+
+\bibitem{TRF-USER}Texas Instruments Incorporated.
+ {\em TRF7960TB HF RFID Reader Module},
+ SLOU297, October 2010.
+ \url{http://www.ti.com/lit/pdf/slou297}
+
+\bibitem{PN512}NXP Semiconductors.
+ {\em PN512 -- Full NFC Forum compliant solution -- Product data sheet},
+ Rev. 4.6, December 2014.
+ \url{http://www.nxp.com/documents/data_sheet/PN512.pdf}
+
+\bibitem{PN512-ANT}NXP Semiconductors.
+ {\em Antenna design guide for MFRC52x, PN51x and PN53x},
+ AN1445, Rev. 1.2, October 2010.
+ \url{http://www.nxp.com/documents/application_note/AN1445_An1444.zip}
+
+\bibitem{PN532-PSDS}NXP Semiconductors.
+ {\em PN532/C1 Near Field Communication (NFC) controller --
+ Product short data sheet},
+ Rev. 3.2, September 2012.
+ \url{http://www.nxp.com/documents/short_data_sheet/PN532_C1_SDS.pdf}
+
+\bibitem{PN532-UM}NXP Semiconductors.
+ {\em UM0701-02 -- PN532 User Manual},
+ Rev. 02, November 2007.
+ \url{http://www.nxp.com/documents/user_manual/141520.pdf}
+
+\bibitem{PN544-OSDS}NXP Semiconductors.
+ {\em PN544 Near field communication (NFC) controller --
+ Objective short data sheet},
+ Rev. 1.2, September 2007.
+
+\bibitem{PN544-ODS}NXP Semiconductors.
+ {\em PN544 Near field communication (NFC) controller --
+ Objective data sheet},
+ Rev. 2.1, December 2008.
+
+\bibitem{AS3910}ams AG.
+ {\em AS3909/AS3910 -- 13.56 MHz RFID Reader IC, ISO-14443 A/B},
+ Version 3-02, October 2013.
+ \url{http://www.ams.com/eng/content/download/371303/1221017/file/AS3909-10_Datasheet_v6.pdf}
+
+\bibitem{AS3911B}ams AG.
+ {\em AS3911B -- NFC Initiator / HF Reader IC},
+ Version 1-08, June 2014.
+ \url{http://www.ams.com/eng/content/download/618303/1666697/file/AS3911B_Datasheet_EN_v1.pdf}
+
+\bibitem{AS3911-DOOR}Luecker, Thomas; Dickson, Mark.
+ {\em AS3911 door handle Hardware description},
+ ams AG, Application note, Rev 1V00, December 2011.
+ \url{http://www.ams.com/eng/content/download/548423/1536317}
+
+%----- CPUs and MCUs ----------------------------------------------------------
+
+\bibitem{DM3730-TRM}Texas Instruments Incorporated.
+ {\em AM/DM37x Multimedia Device -- Technical Reference Manual},
+ SPRUGN4R, Silicon Revision 1.x, Version R,
+ September 2012.
+
+\bibitem{TPS65950}Texas Instruments Incorporated.
+ {\em TPS65950 Integrated Power Management and Audio Codec},
+ SWCS032F, Silicon Revision 1.2, July 2014.
+ \url{http://www.ti.com/lit/ds/symlink/tps65950.pdf}
+
+\bibitem{KL26}Freescale Semiconductor, Inc.
+ {\em Kinetis KL26 Sub-Family -- 48 MHz Cortex-M0+ Based Microcontroller --
+ Data Sheet: Technical Data},
+ KL26P64M48SF5, Rev 5, August 2014.
+ \url{http://cache.freescale.com/files/microcontrollers/doc/data_sheet/KL26P64M48SF5.pdf}
+
+\bibitem{KL26RM}Freescale Semiconductor, Inc.
+ {\em KL26 Sub-Family Reference Manual},
+ KL26P121M48SF4RM, Rev. 3.2, October 2013.
+ \url{http://cache.freescale.com/files/microcontrollers/doc/ref_manual/KL26P121M48SF4RM.pdf}
+
+\bibitem{AN4955}Galda, Michael.
+ {\em Emulating the I2S Bus Master with the FlexIO Module},
+ Freescale Semiconductor, Inc. AN4955, Rev 0, July 2014.
+ \url{http://cache.freescale.com/files/microcontrollers/doc/app_note/AN4955.pdf}
+
+%----- Modem ------------------------------------------------------------------
+
+\bibitem{PHS8E-HW}Cinterion.
+ {\em PHS8-E Hardware Interface Description},
+ PHS8-E\_v03.001, Version 03.001, December 2012.
+
+\bibitem{PHS8P-AT}Cinterion.
+ {\em PHS8-P AT Command Set},
+ PHS8-P\_ATC\_V02.003, Version 02.003, July 2012.
+
+%----- Other ------------------------------------------------------------------
+
+\bibitem{TRF-NFC-COMM}Macias, Erick; Wyatt, Josh.
+ {\em NFC Active and Passive Peer-to-Peer Communication Using the TRF7970A},
+ Texas Instruments Incorporated, SLOA192, April 2014.
+ \url{http://www.ti.com/lit/pdf/sloa192}
+
+%----- To do ------------------------------------------------------------------
+
+\bibitem{NCI}NFC Forum.
+ {\em NFC Controller Interface (NCI); Technical Specification Version 1.1},
+ 2014-07-18.
+ \url{http://members.nfc-forum.org/specs/spec_list/}
+
+\bibitem{HCI}ETSI TS 102 622 V12.0.0 (2013-10).
+ {\em Smart Cards; UICC - Contactless Front-end (CLF) Interface;
+ Host Controller Interface (HCI) (Release 12)},
+ \url{http://www.etsi.org/deliver/etsi_ts/102600_102699/102622/12.00.00_60/ts_102622v120000p.pdf}
diff --git a/nfc/nfc.tex b/nfc/nfc.tex
new file mode 100644
index 0000000..82ed227
--- /dev/null
+++ b/nfc/nfc.tex
@@ -0,0 +1,2445 @@
+\documentclass[11pt]{article}
+\usepackage{a4}
+\usepackage{fullpage}
+\usepackage{fixltx2e}
+\usepackage{graphicx}
+\usepackage{fp}
+\usepackage{xfrac}
+\usepackage{titlesec}
+\usepackage{parskip}
+\usepackage{rotating}
+\usepackage{multirow}
+\usepackage[hang]{footmisc}
+\usepackage{footnote}
+\usepackage[numbib]{tocbibind}
+\usepackage[hidelinks,bookmarksnumbered=true]{hyperref}
+\usepackage[toc,nonumberlist,numberedsection=nolabel,nopostdot]{glossaries}
+
+\bibliographystyle{unsrt}
+\newcommand{\sectionbreak}{\clearpage}
+
+\def\TODO{{\bf TO DO}}
+\def\todo#1{\begin{center}{\bf TO DO:} #1\hfill~\end{center}}
+
+\def\iic{$\hbox{I}^2\hbox{C}$}
+\def\iis{$\hbox{I}^2\hbox{S}$}
+\def\mifare{MIFARE\textsuperscript{TM}}
+\def\felica{FeliCa\textsuperscript{TM}}
+\def\fc{\hbox{$f_C$}}
+\def\fcfrac#1{\sfrac{\hbox{\scriptsize $f_C$}}{\scriptsize #1}}
+\def\fracfc#1{\sfrac{\hbox{\scriptsize #1}}{\scriptsize $f_C$}}
+\def\degree#1{$\hbox{#1}^{\circ}$}
+
+\renewcommand{\footnotemargin}{1.2em}
+
+\def\FPfmt#1{\FPeval{fpfmttmp}{#1}\fpfmttmp{}}
+\def\FPrnd#1#2{\FPfmt{round((#2):#1)}}
+
+\title{Neo900 NFC Subsystem \\
+ {\bf Draft}}
+\author{Werner Almesberger}
+\date{January 5, 2015}
+
+\newenvironment{tab}{\vskip4mm\qquad\begin{minipage}{430pt}}%
+{\end{minipage}\vskip4mm\noindent}
+
+\makeglossaries
+
+\begin{document}
+\maketitle
+
+% Protocols
+
+\newacronym{NFC}{NFC}{Near Field Communication}
+\newacronym{RFID}{RFID}{Radio-Frequency IDentification}
+\newacronym{SWP}{SWP}{Single Wire Protocol}
+
+% Modulation and encoding
+
+\newacronym{AM}{AM}{Amplitude Modulation}
+\newacronym{ASK}{ASK}{Amplitude-Shift Keying}
+\newacronym{BPSK}{BPSK}{Binary \gls{PSK}}
+\newacronym{FSK}{FSK}{Frequency-Shift Keying}
+\newacronym{MFM}{MFM}{Modified Frequency Modulation}
+\newacronym{NRZ}{NRZ}{Non-Return-to-Zero}
+\newacronym{OOK}{OOK}{On-Off Keying}
+\newacronym{PJM}{PJM}{Phase Jitter Modulation}
+\newacronym{PPM}{PPM}{Pulse-Position Modulation}
+\newacronym{PSK}{PSK}{Phase-Shift Keying}
+
+% System elements
+
+\newacronym{CLF}{CLF}{ContactLess Frontend}
+\newacronym{PCD}{PCD}{Proximity Coupling Device}
+\newacronym{PICC}{PICC}{Proximity Integrated Circuit Card}
+\newacronym{SE}{SE}{Secure Element}
+\newacronym{SIM}{SIM}{Subscriber Identity Module}
+\newacronym{UICC}{UICC}{Universal Integrated Circuit Card}
+\newacronym{VCD}{VCD}{Vicinity Coupling Device}
+\newacronym{VICC}{VICC}{Vicinity Integrated Circuit Card}
+
+
+This document specifies the \gls{NFC} and \gls{RFID}
+functionality of Neo900.
+\todo{The focus is currently more on the evaluation and selection of
+suitable technology. We should change this later, when we've decided
+on a specific design.}
+
+Please note that all this is based on reading the relevant standards (or
+drafts of them), data sheets, etc. None of the things described here have
+actually been tested by the author in an implementation.
+
+The document contains a large number of footnotes, acronyms, and citations.
+All these references have hyperlinks in the PDF version,
+which should make it easier to follow them when using the document
+for reference purposes. It is recommended to first read this document
+in its entirety in order to obtain an overview of the various topics
+discussed and how they are related.
+
+% -----------------------------------------------------------------------------
+
+\section{High-level objectives}
+
+We have the following expectations on the NFC solution for Neo900:
+
+\begin{description}
+ \item[Standards]
+ Although we currently have no specific ``must have'' use cases,
+ we aim to be able to interoperate with equipment users will
+ encounter labeled as ``NFC''. In practical terms, this will most
+ likely include
+ NFC Type 2 tags \cite{NFCtag2} (using ISO 14443 Type A \cite{ISO14443}),
+ peer-to-peer communication according to NFC IP-1 \cite{NFCIP1}
+ (using \felica\ \cite{FeliCa} at ``high-speed''),
+ and ISO 14443 card emulation.
+ \item[Flexibility]
+ There are many protocol in the world of NFC and RFID, and any
+ given solution is likely to miss some that may be relevant in certain
+ use cases. We therefore aim to be flexible and give advanced users
+ the option of adapting the NFC functionality of Neo900 to their
+ needs.
+ \item[System environment]
+ The NFC solution must be suitable for the constrained environment
+ found on a mobile phone. This includes the use of
+ system-internal communication interfaces such as \iic\ operating
+ at 1.8 V, low-power standby, and also low power consumption when
+ waiting for the device to enter the field of an NFC or RFID reader.
+ \item[Linux driver]
+ The hardware must have good driver and protocol stack support in
+ Linux, without adding a major development burden to the Neo900
+ project.
+ \item[Hardware documentation]
+ Hardware documentation sufficiently in-depth to enable the Neo900
+ project to correctly implement the NFC circuit must be
+ available -- preferably without NDAs or similar obstacles.
+ \item[Privacy]
+ In line with our general emphasis on privacy and user empowerment,
+ we aim to ensure that the NFC subsystem will not communicate without
+ the user's express consent. In particular, it must either lack the
+ ability of field-powered operation or there must be a mechanism that
+ allows users to suppress this mode of operation.
+ \item[Tweakable]
+ Wherever practical, advanced users should be given access to low
+ protocol layers not only in order to allow the addition of support
+ for new protocols, as mentioned above, but also for experiments with
+ the design and implementations of the protocols themselves.
+\end{description}
+
+% -----------------------------------------------------------------------------
+
+\section{Communication modes}
+
+This section gives a very brief introduction to the communication modes
+used in the context of NFC/RFID with the following drawings illustrating the
+various scenarios.
+
+The ``reader'' is also called ``reader/writer'', and in the various ISO
+standards \gls{PCD}, \gls{VCD}, or ``interrogator''. The ``card'' is
+often called a ``tag'', and ISO also uses \gls{PICC} and \gls{VICC}.
+We will use mainly the terms ``reader'' and ``card'' or ``tag''.
+
+
+\subsection{Reader and card}
+
+The basic model is to have a reader and a card or tag.
+The reader is connected to a power source, is often part of a fixed
+installation, and generates a strong electromagnetic field whenever it is
+looking for cards (which it may be expected to do most of the time).
+
+The card is mobile and has no power source of its own. Instead, it is
+powered by the field the reader generates. A the card that is not near a
+reader receives no power and is therefore not operational.
+
+\begin{center}
+\includegraphics[scale=0.9]{comm-rw-rdr.pdf}
+\qquad
+\includegraphics[scale=0.9]{comm-rw-card.pdf}
+\end{center}
+
+The reader sends data to the card (drawing on the left) by modulating
+the field it emits. It typically uses some form of \gls{AM}, though
+other modulation schemes are possible.
+The card sends data to the reader (drawing on the right) by changing
+the characteristics of its receiver and thus modulating the field
+created by the reader. This is called load modulation.
+
+If there are multiple cards in the vicinity of a reader, their
+transmissions may overlap (``collide'') and the reader therefore has to
+select a single one for communication. This process is called
+``anti-collision'' and is described in more detail in section
+\ref{anticoll}.
+
+
+\subsection{Card structure}
+
+In addition to the radio interface and associated protocol processing,
+an NFC/RFID card contains also additional elements, as shows in the following
+drawing:
+
+\begin{center}
+\includegraphics[scale=0.9]{card.pdf}
+\end{center}
+
+In a very simple application, a card will just have a unique ID (UID)
+and a reader merely queries this ID. A more sophisticated application
+would use a challenge-response scheme to prevent others from impersonating
+the card.
+
+A card can have additional memory that can be read and possibly also
+written by the reader (or reader/writer). Such memory can for instance
+contain publicly accessible information such as a product code, a URL,
+an image, etc.
+
+Last but not least, a card may contain a \gls{SE}. This is provides an
+isolated execution environment for security-sensitive applications, such
+as authentication protocols for electronic payment.
+
+
+\subsection{Card emulation}
+
+Card emulation is similar to the previous scenario, except that we have
+a smartphone in the role of a card. The smartphone may use its own power
+source but its NFC/RFID subsystem may also be capable of operating with
+power from the field alone.
+
+\begin{center}
+\includegraphics[scale=0.9]{comm-ce-rdr.pdf}
+\end{center}
+
+Communication is exactly the same as with a card: the reader modulates
+the field to send data to the phone, and the phone modulates the field
+by changing its load characteristics to respond.
+
+\begin{center}
+\includegraphics[scale=0.9]{comm-ce-card.pdf}
+\end{center}
+
+If the application requires a \gls{SE}, then this may be provided
+either as part of the smartphone's hardware, by software, or through a
+\gls{SIM} card. In the latter case, the NFC/RFID subsystem acts merely
+as a relay between the radio interface and the SIM card, with the \gls{SE}
+controlling most of the protocol processing.
+We discuss the mechanism used for communication between the secure
+element in the SIM card and the smartphone in section \ref{swp}.
+
+Note that a smartphone can also act as reader, communicating with a
+card or with another smartphone using card emulation.
+
+
+\subsection{NFC peer-to-peer}
+
+When both parties are smartphones or similar devices, they can also
+use NFC peer-to-peer communication. Unlike a card reader that will
+typically continuously scan for cards, an NFC device only activates
+its field when requested to do so. A device can act as ``initiator''
+(activates field and then searches for peer) or as ``target''
+(wait for an initiator to begin communicating).
+
+\begin{center}
+\includegraphics[scale=0.9]{comm-p2p-init.pdf}
+\end{center}
+
+Communication between initiator and target can be as if they were reader
+and card, respectively, with the initiator providing the field and the
+target modulating it. The main difference is that the target has its own
+power supply and thus does not depend on the presence of an initiator to
+operate.
+
+\begin{center}
+\includegraphics[scale=0.9]{comm-p2p-tpas.pdf}
+\end{center}
+
+The above is called ``passive'' mode. Since both devices are capable
+of producing an electromagnetic field, there is also an ``active'' mode,
+depicted below.
+
+\begin{center}
+\includegraphics[scale=0.9]{comm-p2p-tact.pdf}
+\end{center}
+
+In this mode, the initiator deactivates its field when it is done sending
+and the target generates its own field to send a response. I.e., this is
+how radio communication normally works, with each party providing the
+electromagnetic field needed for its transmissions.
+
+
+% -----------------------------------------------------------------------------
+
+\section{Protocol architecture}
+
+There are four major protocol families in NFC:
+
+\begin{description}
+ \item[RFID] for ``dumb'' tags, defined in ISO 18000 \cite{ISO18000-3}.
+ \item[Proximity cards] with a range of up to about 10~cm,
+ defined in ISO 14443 \cite{ISO14443-2,ISO14443-3,ISO14443-4}.
+ \item[Vicinity cards] with a range of up to about 1~m,
+ defined in ISO 15693 \cite{ISO15693-2,ISO15693-3}.
+ \item[NFC] for tags \cite{NFCtags} but also for devices that can act as
+ equals, defined in \cite{NFCIP1}.
+ NFC also covers interoperation with the above standards, in \cite{NFCIP2}.
+\end{description}
+
+All four stacks are based on the 13.56 MHz ISM band. Each then defines
+a modulation and encoding scheme. We briefly discuss these in section
+\ref{modenc}. At the next layer are framing and anti-collision, which
+we cover extensively in section \ref{anticoll}.
+On top of everything is the actual user of the stack, which
+may in turn be another stack of more protocols.
+
+The following diagram shows the overall structure of the NFC protocol
+stack, with protocol variants within the same family and relations
+between families:
+
+\begin{center}
+\includegraphics[scale=0.8]{stack.pdf}
+\end{center}
+
+Where protocols are shared across families, the origin of the protocol
+is shown with a grey background. For example, ISO 18000-3 Mode 1 without
+extensions uses the anti-collision protocol defined in ISO 15693-3.
+Proprietary protocol variants like \mifare\ or \felica\ are not shown.
+
+% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+\subsection{Names and aliases of standards}
+
+The ISO standards often have names of the form
+{\em standard\_family}--{\em part}. In the case of ISO 14443, the numbering
+of the parts (--2 to --4) could be misunderstood as representing OSI
+layering. This is not the case, and as the example of ISO 18000 shows,
+the same standard document may cover layers that are split into multiple
+parts in a different family.
+
+Furthermore, protocol variants described in the same standards document
+can be radically different from each other and do not have to be
+interoperable. For example, it is perfectly acceptable for a
+standards-compliant ISO 18000-3 Mode 1 device to be unable to communicate
+with a standards-compliant ISO 18000-3 Mode 2 device.%
+\footnote{Emphatically stated several times in sections 1.3,
+6.0.1 to 6.0.4, 6.1, and 6.2 of \cite{ISO18000-3}.}
+
+According to \cite{TI14443}, the division of ISO 14443 into an A and a B
+type mirrors the two competing advocates, NXP (type A) and Texas Instruments
+(type B). Sony unsuccessfully tried to establish an ISO 14443 Type C and
+then created \felica\ (similar to ISO 14443-2 Type B with
+ISO 14443-3 Type A annex C on top).
+
+Some standards go by many names. For instance, NCF IP-1 \cite{NFCIP1} is
+known as ISO/IEC 18092 and ECMA-340, and one of the protocol variants it
+specifies ($\fc/128$) just reuses ISO/IEC 14443 Type A for its lower
+layers. Also note that ISO 18092 (NFC) is very different from ISO 18000
+(RFID tags).
+
+Among other protocols, \cite{NFCdigital} specifies the
+following underlying standards for protocols of the various tag types
+defined by NFC Forum:
+
+\begin{tab}
+\begin{tabular}{cc|ll}
+ Type & & Basis & Standard \\
+ \hline
+ 1 & \cite{NFCtag1} & NFC-A & NFC IP-1 \cite{NFCIP1},
+ meaning ISO 14443 Type A \\
+ 2 & \cite{NFCtag2} & NFC-A & NFC IP-1 \cite{NFCIP1},
+ meaning ISO 14443 Type A \\
+ 3 & \cite{NFCtag3} & NFC-F & NFC IP-1 \cite{NFCIP1}, meaning \felica \\
+ 4A & \cite{NFCtag4} & NFC-A & NFC IP-1 \cite{NFCIP1},
+ meaning ISO 14443 Type A \\
+ 4B & \cite{NFCtag4} & NFC-B & ISO 14443 Type B \\
+\end{tabular}
+\end{tab}
+
+% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+\subsection{Bit rates}
+
+Timings in NFC are usually expressed in terms of the carrier frequency
+$\fc=13.56~\rm MHz$, with subcarrier frequencies and data rates using the
+notation
+\fcfrac{n} and bit durations \fracfc{n}.
+
+The following table shows the most commonly used rates, the corresponding
+bit durations, and also mentions the most relevant standard(s) using
+that rate:
+
+\FPeval{ffc}{13560} % 13560 kHz
+
+\def\rate#1#2#3{\FPfmt{#1} & \FPrnd{#2}{ffc/(#1)} & \FPrnd{#3}{(#1)*1000/ffc}}
+
+\begin{tab}
+\begin{tabular}{c|cc|l}
+ Divider $n$ & Bit rate & Bit duration & Used by $\ldots$ \\
+ & \fcfrac{n} & \fracfc{n} \\
+ & kbps & $\mu s$ \\
+ \hline
+ \strut
+ \rate{2048}{2}{0} & ISO 15693, low rate, single subcarrier \\
+ \rate{2032}{2}{0} & \qquad dual subcarrier \\
+ \rate{512}{2}{0} & \quad high rate, single subcarrier \\
+ \rate{508}{2}{0} & \qquad dual subcarrier \\
+ \rate{128}{0}{2} & ISO 14443 \\
+ \rate{64}{0}{2} & ISO 14443 (after anti-collision), \felica \\
+ \rate{32}{0}{2} & ISO 14443 (after anti-collision) \\
+ \rate{16}{0}{2} & ISO 14443 (after anti-collision) \\
+\end{tabular}
+\end{tab}
+
+NCF IP-1 stretches the rules of \felica%
+\footnote{Sections 5.2.1 and 5.3.1 of \cite{FeliCa}.}
+a little and allows rates up to \fcfrac{32}.%
+\footnote{Section 9.2.2.1 of \cite{NFCIP1}.}
+
+% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+\subsection{Modulation and coding}
+\label{modenc}
+
+In this section we briefly summarize the lower layers of NFC radio
+protocols. This overview is intended to provide context for the following
+sections and also to better understand the capabilities and limitations of
+the chips we examine later on.
+
+All RFID/NFC devices in the HF band operate with a carrier
+frequency of 13.56 MHz $\pm$ 7 kHz.
+
+Since the RF field of the reader also provides power to cards, the
+communication protocols used in the reader to card direction try to
+keep the field reasonably constant:
+
+\begin{tab}
+\begin{tabular}{ll|ll}
+ Protocol & Variant & Modulation & Coding \\
+ \hline
+ ISO 14443-2 & Type A & \glstext{ASK} 100\% & modified Miller \\
+ & Type B & \glstext{ASK} 10\% & \glstext{NRZ} \\
+ ISO 15693-2 & \fracfc{256} & \glstext{ASK} 10 or 100\%
+ & \glstext{PPM} \sfrac{1}{256} \\
+ & \fracfc{4} & ditto & \glstext{PPM} \sfrac{1}{4} \\
+ ISO 18000-3 & Mode 1 & \multicolumn{2}{l}{see ISO 15693-2} \\
+ & Mode 2 & \glstext{PJM} & \glstext{MFM} \\
+ \felica & & \glstext{ASK} 10\% & Manchester \\
+ NFC IP-1 & \fcfrac{128} & \multicolumn{2}{l}{see ISO 14443-2 Type A} \\
+ & other & \multicolumn{2}{l}{see \felica} \\
+\end{tabular}
+\end{tab}
+
+In the opposite direction, the card uses load modulation and the protocols
+typically aim to produce a stable regular pattern throughout each bit
+duration:
+
+\begin{tab}
+\begin{tabular}{ll|ll}
+ Protocol & Variant & Modulation & Coding \\
+ \hline
+ ISO 14443-2 & Type A, \fcfrac{128} & \glstext{OOK} & Manchester \\
+ & other & \glstext{BPSK} & \glstext{NRZ} \\
+ ISO 15693-2 & single subcarrier & \glstext{OOK} & --- \\
+ & dual subcarrier & \glstext{FSK} & --- \\
+ ISO 18000-3 & Mode 1 & \multicolumn{2}{l}{see ISO 15693-3} \\
+ & \quad extensions & \glstext{BPSK}/\glstext{OOK} & --- \\
+ & Mode 2 & \glstext{BPSK} & \glstext{MFM} \\
+ \felica & & \glstext{OOK} & Manchester \\
+ NFC IP-1 & \fcfrac{128} & \multicolumn{2}{l}{see ISO 14443-2 Type A} \\
+ & other & \multicolumn{2}{l}{see \felica} \\
+\end{tabular}
+\end{tab}
+
+% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+\subsection{Anti-collision}
+\label{anticoll}
+
+Anti-collision is the process of identifying individual cards or tags
+(\gls{PICC} or \gls{VICC})
+in a set of cards or tags
+that have been brought into the RF field of a reader
+(\gls{PCD} or \gls{VCD}),
+and then activating one or more specific
+cards for further communication.
+
+This section summarizes the anti-collision mechanisms used by the
+protocols specified for RFID and NFC. The main objectives are to
+provide a rough overview of the variety of protocols and
+to determine -- at a qualitative level -- what kind of timing
+requirements would exist for software
+implementations of the respective protocols.
+
+We pay special attention to anti-collision since this is the part of
+the various NFC and RFID protocols that is most likely to involve
+delicate timing (e.g., precise detection of collisions at the bit
+level, see section \ref{anticoll14443-3a}) and complex modulation
+schemes (e.g., \gls{OOK} and \gls{PSK} in the same message, see section
+\ref{anticoll18000-3.1}). This in turn determines what hardware
+capabilities we require from NFC chips in order to handle a given
+protocol, and what software-based solutions have to do if trying to
+support a protocol that is not fully supported by hardware.
+
+
+\subsubsection{ISO 14443-3 type A}
+\label{anticoll14443-3a}
+
+ISO 14443-3 type A uses an anti-collision algorithm where cards whose
+addresses match a prefix provided by the reader respond by sending their
+(unique) addresses bit-synchronously. The reader detects
+collisions at the bit level, grows the prefix accordingly, and repeats
+this process until one card has been fully identified.
+
+For example, a reader would first initiate the anti-collision sequence
+by sending an REQA or WUPA command, to which all suitable type A cards
+respond with an ATAQ message. The reader would then send an
+ANTICOLLISION (AC) command with a prefix of length zero. All cards
+simultaneously
+respond with their addresses, producing collisions on some bit
+positions. The reader adds the collision-free bits to the prefix,
+picks 0 or 1 for the next bit, and sends a new AC command for the
+new prefix. This is illustrated in the following diagram where cards
+A and B match the prefix but then collide in the last two bits:
+
+\begin{center}
+\includegraphics[scale=0.9]{prefix.pdf}
+\end{center}
+
+From a card's point of view, the sequence ends when the prefix
+matches the entire address of the card (in which case the AC command is
+called SELECT) and the card then acknowledges this with a SAK (select
+acknowledge) response.
+
+The protocol is described in detail in sections 6.3 through 6.5 of
+\cite{ISO14443-3}.
+
+
+\subsubsection{ISO 14443-3 type B}
+\label{anticoll14443-3b}
+
+ISO 14443-3 type B uses a slotted anti-collision mechanism where the
+effect of collisions can be observed at the frame level.
+
+The reader begins each anti-collision sequence by sending a WUPB(N) or
+REQB(N) command with parameter $1 \le N \le 16$. Each card then picks
+an individual random number $1 \le R \le N$. If $R=1$, it immediately
+sends an ATRB response, possibly colliding with responses from
+other cards. The reader can then send slot markers SM(s)
+for $2 \le s \le N$ to which cards respond if $R=s$ (using the random
+number generated upon reception of WUPB/REQB).
+
+The reader can suppress further anti-collision responses from a card by
+activating it with ATTRIB or by silencing further responses to REQB with
+the command HLTB. The reader performs the anti-collision sequence
+whenever it is looking for new cards or when
+trying to enumerate a set of cards that has entered its RF field.
+
+The protocol is described in detail in sections 7.3 through 7.10
+of \cite{ISO14443-3}
+and more accessibly in Atmel's excellent summary \cite{Atmel2056B}.
+Atmel also expands that this mechanism exists in two flavours,
+probabilistic%
+\footnote{As shown in the example in annex D of \cite{ISO14443-3}.}
+and slotted, which differ in whether the reader sends slot markers to
+probe cards with $R>1$ or whether it just uses successive random number
+draws until every card has chosen $R=1$ and thus responded in the first
+slot.
+
+
+\subsubsection{ISO 14443-3 type A annex C}
+\label{anticoll14443-3ac}
+
+Not to be outdone by type B, type A also has an optional slotted
+anti-collision protocol, described in annex C of \cite{ISO14443-3}.
+Like in type B, cards respond in randomly selected time slots, but
+with the difference that time slots are not explicitly signaled by
+the reader but instead determined by the time that has passed since
+the REQ-ID command that starts the whole time slot sequence.
+
+While there is no direct command to silence a card, a card that has been
+identified and activated will remain silent after concluding operation
+according to ISO 14443-4.%
+\footnote{Section C.3 of \cite{ISO14443-3}, and also shown in figure
+C.1 in section C.5.}
+
+
+\subsubsection{FeliCa}
+\label{anticoll14443-felica}
+
+\felica\ \cite{FeliCa} has basically the same anti-collision protocol as
+ISO 14443-3 type A annex C (section \ref{anticoll14443-3ac}), but with
+a different message structure and a reduced set of message types.
+
+
+\subsubsection{ISO 15693-3}
+\label{anticoll15693-3}
+
+The anti-collision mechanism defined in section 8 of
+ISO 15693-3 \cite{ISO15693-3} combines a prefix mechanism with
+slots. Like in ISO 14443-3 type A (section \ref{anticoll14443-3a}),
+the reader sends an inventory request containing a prefix for the
+card ID. The cards with matching addresses then respond with their
+full ID in the respective slot corresponding to the four bits of their
+ID that follow the
+prefix. This is similar to ISO 14443-3 type A annex C (section
+\ref{anticoll14443-3ac}), except that the slot number is not random.
+
+Collisions are detected at the frame level in each slot.
+Slot numbers are not explicitly signaled by the
+reader, but instead each card keeps a local slot counter and
+increments it when the end of a slot is indicated. If a card sees more
+slots being signaled than expected in a round, it simply ignores
+the extra slots.%
+\footnote{Figure 9 in section 8.2 of \cite{ISO15693-3}.}
+
+Besides the ``Inventory'' command, there are also the usual commands
+for resetting the anti-collision protocol state (``Reset to ready''),
+to silence a specific card (``Stay quiet''), and to select a card
+for further communication (``Select'').%
+\footnote{Sections 9.2.1, 9.3..7, 9.2.2, and 9.3.6 of \cite{ISO15693-3},
+respectively.}
+
+Card selection is not required for communication but allows to omit
+the card's ID in further messages.%
+\footnote{Section 7.2.3 of \cite{ISO15693-3}.}
+
+
+\subsubsection{ISO 18000-3 mode 1}
+\label{anticoll18000-3.1}
+
+ISO 18000-3 mode 1 uses ISO 15693-3 anti-collision%
+\footnote{Section 6.1.2 of \cite{ISO18000-3}. ISO 15693 is included
+in ISO 18000-3 as annex G.}
+but also features a protocol extension that comes in two major
+branches called ``non-slotted non-terminating multiple tag reading''
+and ``slotted terminating adaptive round multiple tag reading''.%
+\footnote{Sections 6.1.10.2 and 6.1.10.4 of \cite{ISO18000-3}.}
+
+
+\paragraph{Non-slotted extension}
+
+The non-slotted extension is refreshingly simple and consists of
+a Wake-up%
+\footnote{Section 6.1.11.2.13 of \cite{ISO18000-3}.}
+command from the reader, which then causes tags to send their
+default replies%
+\footnote{Sections 6.1.10.16 and 6.1.10.17 of \cite{ISO18000-3}.}
+randomly and repeatedly as long as they remain in the field.
+While timing is not specified, it is recommended that
+$\frac{\hbox{\footnotesize \strut Time between replies}}%
+{\hbox{\footnotesize\strut Duration of reply}}\approx 10$.
+The reader simply
+listens for any responses and uses those that are not garbled.
+
+
+\paragraph{Slotted extension}
+
+The slotted extension is somewhat similar to ISO 14443-3 type B
+(section \ref{anticoll14443-3b}) in that cards respond in randomly
+selected slots and that slots are explicitly announced by the reader.
+
+Like in ISO 15693-3, cards keep a local slot count that advances at
+the end of the slot.
+It differs in that
+slot counters of tags wrap around -- with the drawing of a new
+random number -- at the highest slot number. Different
+tags may use different highest slot numbers, but the reader can
+also command a common slot number range.%
+\footnote{The general sequence is defined in sections 6.1.10.4 and
+6.1.10.7 of \cite{ISO18000-3}. The commands are defined in the
+following sections:
+Wake-up (begins a round), 6.1.11.2.12;
+Next-slot, 6.1.11.2.1 through 6.1.11.2.3;
+New-round-size (sets new highest slot number and resets the slot
+counters in tags), 6.1.11.2.16.}
+
+A reader responding in a slot sends a two-part response consisting
+of a so-called precursor used for collision detection,%
+\footnote{Message sequence in section 6.1.10.10, precursor format in
+6.1.10.12, \gls{PSK} of sub-carrier for the leader in section
+6.1.10.18.2,
+and \gls{OOK} for the collision detection sequence in
+sections 6.1.10.18.3 and 6.1.10.18.4.}
+followed by the actual response.%
+\footnote{Sections 6.1.10.10 and 6.1.10.11 for the message sequence,
+6.1.10.16 and 6.1.10.17 for the main reply format, \gls{PSK}
+in section 6.1.10.19.}
+
+If a collision is detected, the reader can either end the slot after
+the precursor (the cards have to turn around and listen between
+precursor and main reply) or by indicating an error at the end of
+the regular slot duration.%
+\footnote{Explained in section 6.1.10.5, the ``ultimate-error'' command
+is described in section 6.1.11.2.7.}
+While the timing of whole slots is provided by messages sent by the
+reader, the phases inside a slot (i.e., precursor, possible early
+termination, main reply) are determined by the time since the beginning
+of the slot.%
+\footnote{Figure 4 and table 2 in section 6.1.10.5 of \cite{ISO18000-3}.}
+
+
+\subsubsection{ISO 18000-3 mode 2}
+
+ISO 18000-3 mode 2 is designed to work with very large tag populations
+in the same field%
+\footnote{Table 26 in section 6.2.6 of \cite{ISO18000-3} mentions a
+tag inventory of more than 32\,000 tags.}
+and differs substantially from all the above protocols.
+It uses a novel modulation scheme for a single communication channel from
+the reader to cards,%
+\footnote{\Gls{PJM}, see annex A of \cite{ISO18000-3}.}
+and eight reply channels distinguished by their subcarrier frequencies
+for card responses.%
+\footnote{Section 6.2.3.3.1 of \cite{ISO18000-3}.}
+Readers may receive on all eight channels simultaneously but can
+also support only operation on a single channel.%
+\footnote{Section 6.2.7.3.1, example in section 6.2.7.8.
+Single channel selection is described in table 20 in section 6.2.5.16.3.2.}
+Last but not least, tags can be randomly muted%
+\footnote{Section 6.2.7.3.2.2, example in section 6.2.7.9.}
+or they can be individually ordered to remain silent.%
+\footnote{``Fully muted'' in section 6.2.7.3.2, ``temporarily muted''
+in the example in section 6.2.7.8. The mechanism for putting a tag in
+fully muted state is described in section 6.2.5.16.7, the corresponding
+code point is in table 20 of 6.2.5.16.3.2.}
+
+There are only two command types: read and write. There is no slotting.
+
+
+\subsubsection{ISO 18000-3 mode 3}
+
+A third mode was added to ISO 18000-3, for which no freely available
+information could be found.
+
+
+\subsubsection{NFC IP-1}
+
+An NFC initiator performs CSMA/CA, i.e., it can activate its RF field
+only if it does not detect the presence of another field.%
+\footnote{Section 11.1.1 of \cite{NFCIP1}.}
+This is called ``RF collision avoidance.''
+
+In passive mode, this only affects access to the ether, but in active
+mode, RF collision avoidance is also used for selecting a target
+(i.e., the one with the shortest random delay).%
+\footnote{Section 11.3 of \cite{NFCIP1}.}
+
+In passive mode at \fcfrac{128}, NFC uses ISO 14443-3 type A anti-collision
+(section \ref{anticoll14443-3a}) with a new codepoint indicating NFC in
+the SAK message sent by the NFC target.%
+\footnote{Section 11.2.1 of \cite{NFCIP1}.}
+
+In passive mode at \fcfrac{64} and \fcfrac{32}, NFC uses \felica.%
+\footnote{Section 11.2.2 of \cite{NFCIP1}.}
+
+
+\subsubsection{Summary}
+
+The following table summarizes the key characteristics of the
+various anti-collision mechanisms:
+
+\begin{tab}
+\begin{tabular}{ll|ll}
+ Protocol & Variant & Separation & Time-based \\
+ \hline
+ ISO 14443-3 & Type A & Prefix & Bit collision \\
+ & Type B & Random slot & --- \\
+ & Annex C & Random slot & Slot \\
+ \felica & & Random slot & Slot \\
+ ISO 15693-3 & & Prefix, deterministic slot & --- \\
+ ISO 18000-3 & Mode 1 & \multicolumn{2}{l}{see ISO 15693-3} \\
+ & \quad non-slot extension & Random delay & --- \\
+ & \quad slot extension & Random slot & Phase in slot \\
+ & Mode 2 & Random channel, mute & --- \\
+ NFC IP-1 & \fcfrac{128} & \multicolumn{2}{l}{see ISO 14443-3 Type A} \\
+ & other & \multicolumn{2}{l}{see \felica} \\
+\end{tabular}
+\end{tab}
+
+``Separation'' is what prevents multiple cards from always replying at
+the same time. ``Time-based'' describes the element of the anti-collision
+protocol that has the tightest timing requirements.
+
+% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+\subsection{Framing}
+
+Framing of messages in the various NFC protocols is not covered in
+this document. The chips we discuss later implement some types of framing
+in hardware and usually provide some form of ``raw'' access to the radio
+interface to allow external digital hardware to implement codings and
+framings the respective NFC chip does not support natively.
+
+% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+\subsection{Higher layers}
+
+There can be many additional protocol layers on top of anti-collision and
+framing, particularly in the case of NFC peer-to-peer operation.
+See for example figure 1 in section 1 of \cite{TRF-NFC-COMM},
+with additional details in figure 14 in section 6.%
+\footnote{The same document also serves as a warning against overly
+ optimistic expectations regarding interoperability: the experimental
+ results in section 9 show that the chances for successful peer-to-peer
+ communication with contemporary smartphones were rather low when using
+ anything other than NFC-F and the smartphone acting as initiator.}
+``Smart'' NFC chips may implement some elements from these
+protocols while ``dumb'' chips will just pass frames to the host and
+let it take care of the rest.
+
+% -----------------------------------------------------------------------------
+
+\section{Available protocol stacks}
+
+A surprisingly large number of NFC stacks is available for Linux.
+They can be characterized as follows: \cite{LinuxNFC2011}
+
+\begin{description}
+ \item[libnfc-nxp]
+ NXP-centric vendor stack for Android. \\
+ \url{https://android.googlesource.com/platform/external/libnfc-nxp/}
+ \item[Open NFC]
+ Another vendor stack, this time from Inside Secure. \\
+ \url{http://open-nfc.org/}
+ \item[librfid]
+ The user-space stack of the OpenPCD project. Now defunct and
+ replaced by libNFC. \\
+ \url{http://www.openpcd.org/Host_Software#librfid}
+ \item[libNFC]
+ Community project developing a user-space stack centered on the
+ NXP PN53x chip family.%
+\footnote{\url{http://nfc-tools.org/index.php?title=Devices_compatibility_matrix}} \\
+ \url{http://nfc-tools.org/}
+ \item[Linux NFC]
+ Kernel-based vendor-neutral (at the time of writing, the stack had
+ drivers for devices from Inside Secure, Marvell, NXP, Sony, STM, and
+ Texas Instruments)
+ stack, following the regular development
+ model for the Linux kernel. \\
+ \url{https://01.org/linux-nfc}
+\end{description}
+
+The kernel-based Linux NFC project clearly looks like the future and
+we can probably safely ignore the other projects.
+
+% -----------------------------------------------------------------------------
+
+\section{Neo900 hardware architecture}
+
+The following drawing shows the overall structure of the part of the
+Neo900 architecture we're concerned with here:
+
+\begin{center}
+\includegraphics[scale=0.9]{sys.pdf}
+\end{center}
+
+Modem and NFC subsystem both access the \gls{SIM} cards through a switch
+that distributes data signals and power from both sources to the
+cards. The modem communicates with the protocol defined in
+\cite{UICC}, while the NFC subsystem uses the \gls{SWP}
+defined in \cite{SWP}. Both protocols share
+the same power rails but use different signals for communication.
+
+Coordination between CPU, NFC subsystem, and the switch is not defined
+yet, which is indicated with a dashed line.
+
+Further details on \gls{SIM} card switching is outside of the scope of
+this document and may be addressed in a separate publication.
+For simplicity, in the remainder of this document, we will assume
+that only one \gls{SIM} card is present in the system.
+
+The card or tag is commonly known as \gls{SIM} but
+is also called \gls{UICC} in ISO
+parlance, and when the context is unambiguous, we may simply refer
+to it as ``card'' or ``tag''. The system's main CPU, the TI DM3730,
+is sometimes also called ``host''.
+The NFC subsystem is called \gls{CLF}
+in \cite{SWP}. We will use the terms \gls{UICC} and \gls{CLF} only
+rarely in this document, but the reader will encounter them when
+following some of the references.
+
+The entire ``phone'' is -- from the \gls{SIM} card's point of view -- a
+``terminal''.
+
+
+% -----------------------------------------------------------------------------
+
+\def\vcc{V\textsubscript{CC}}
+\def\voh{V\textsubscript{OH}}
+\def\vol{V\textsubscript{OL}}
+\def\vih{V\textsubscript{IH}}
+\def\vil{V\textsubscript{IL}}
+
+\section{SWP}
+\label{swp}
+
+As its name suggests, the Single Wire Protocol consists of a single
+wire (called SWIO) connecting the NFC subsystem and the \gls{SIM}:
+
+\begin{center}
+\includegraphics[scale=0.9]{swp.pdf}
+\end{center}
+
+The lower layers of \gls{SWP} are defined in \cite{SWP}.
+It is intended to convey configuration data and radio messages related
+to ISO 14443-3 type A
+\cite{ISO14443-3} and NFC IP-1 \cite{NFCIP1} between NFC and the Secure
+Element in the \gls{SIM}.
+
+Bidirectional communication is made possible over this single wire by
+using voltage signaling (signal S1) from NFC to \gls{SIM}, and current
+signaling (signal S2) from \gls{SIM} to NFC. Section \ref{swptime}
+contains a detailed illustration of this process.
+
+% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+\subsection{Voltages}
+
+The supply voltage of the \gls{SIM} card for \gls{SWP} use has to be%
+\footnote{Section 7.1.1 of \cite{SWP}.}
+either class B or C, which are defined as 2.7--3.3 V and 1.62--1.98 V,
+respectively.%
+\footnote{Sections 5.2.1 and 5.3.1 of \cite{UICC}.}
+The voltage on SWIO is confusingly defined as either absolute (class B and
+sometimes class C) or relative to \vcc\ (class C).%
+\footnote{Tables 7.3 and 7.4 in section 7.1.3 of \cite{SWP}.}
+The following table summarizes the voltage levels at the card interface,
+for simplicity assuming \vcc\ in class C to be exactly 1.8 V:
+
+\begin{tab}
+\begin{tabular}{cc|cc|cc}
+ Voltage & Class & \multicolumn{2}{c}{Absolute (V)} &
+ \multicolumn{2}{c}{$\times$ 1.8 V} \\
+ & & Min & Max & Min & Max \\
+ \hline
+ \voh & B & \bf 1.40 & \bf 1.98 & 0.78 & 1.1 \\
+ & C & 1.53 & 1.8 & \bf 0.85 & \bf 1 \\
+ \vol & B & \bf 0 & \bf 0.3 & 0 & 0.17 \\
+ & C & 0 & 0.27 & \bf 0 & \bf 0.15 \\
+ \hline
+ \vih & B & \bf 1.13 & \bf 2.28 & 0.63 & 1.27 \\
+ & C & 1.26 & \bf 2.1 & \bf 0.7 & 1.17 \\
+ \vil & B & \bf --0.3 & \bf 0.48 & --0.17 & 0.27 \\
+ & C & \bf --0.3 & 0.45 & --0.17 & \bf 0.25 \\
+\end{tabular}
+\end{tab}
+
+Values defined by the standard are shown in boldface, the other values
+are calculated. Note that \vih\ must be guaranteed for currents up to
+1000 $\mu$A (into the card) and \vil\ for currents up to $\rm -20~\mu A$.%
+\footnote{Table 7.5 in section 7.1.4.1 of \cite{SWP}.}
+
+It is confusing that the standard would specify output and input
+voltages, given that SWIO is voltage-operated in one direction and
+current-operated in the other, and one would therefore expect input
+and output to be identical as far as voltages at this interface are
+concerned.
+
+% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+\subsection{SWIO states}
+\label{swpstates}
+
+We can combine the worst-case voltage requirements from above with
+the possible states of S1 and S2 and the corresponding currents
+that may flow:
+
+\begin{tab}
+\begin{tabular}{cc|cc}
+ S1 & S2 & Voltage (V) & Current ($\mu$A) \\
+ \hline
+ L & --- & $< 0.27$ & $\le 20$ \\
+ H & 0 & $\ge 1.53$ & $\le 20$ \\
+ H & 1 & $\ge 1.53$ & 600--1000 \\
+\end{tabular}
+\end{tab}
+
+For example, the interpretation of S1=H, S2=1 is that the host must
+be able to detect an S2=0 condition if the card draws at least
+600 $\mu$A, and that the voltage at the card's SWIO pin must be at
+least 1.53 V if the card draws up to 1 mA.
+
+Note that these worst-case requirements are probably too strict and
+lead to an operating point very close to the supply voltage .
+If we decide to use more relaxed bounds, the circuit will be able
+to have larger tolerances margins.
+
+% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+\subsection{SWP bit encoding}
+\label{swptime}
+
+\newcommand*\rfrac[2]{{}^{#1}\!/_{#2}}
+
+The default bit duration is 1--5 $\mu$s.\footnote{Table 8.1 in section
+8.1 of \cite{SWP}.}
+Each bit period begins with a rising edge on SWIO and a high level of
+$\rfrac{1}{4}$ (to send a ``0'' on S1) or $\rfrac{3}{4}$ (to send a ``1'),
+followed by the falling edge and a low level until the end of the
+bit period.
+
+The following diagram illustrates transmission on S1 and S2.
+For simplicity, we use a nominal bit time of $4~\mu$s,
+a nominal voltage of 1.8 V,
+and a nominal high current of 800 $\mu$A ($800\pm 200~\mu$A).
+
+\begin{center}
+\includegraphics[scale=0.9]{swp-t.pdf}
+\end{center}
+
+The card switches its load characteristics while SWIO is low, and
+the state of S2 is only defined while SWIO is high. Further details can
+be found in section 8 of \cite{SWP}.
+
+Depending on implementation constraints, one may prefer a faster or a
+slower bit rate than indicated in the example above. A low rate may
+be preferable if the CPU is unable to toggle IO pins quickly or if
+measuring
+the S2 signal is slow. A fast rate may be preferable for more rapid
+communication and if there are large positive delay variations on CPU
+operations,
+e.g., caused by background activity such as cache or DMA operations.
+
+% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+\subsection{S2 current detection}
+\label{swpcmp}
+
+Devices what would allow direct detection of currents that result
+in only small voltage changes are not commonly available in SoCs or
+MCUs. A simple circuit to measure the S2 current would involve a
+series resistor on SWIO that acts as shunt, and an analog comparator
+or similar that compares the resulting voltage drop against a
+threshold voltage. The following diagram shows a common configuration
+of such a circuit:
+
+\begin{center}
+\includegraphics[scale=0.9]{swp-cmp.pdf}
+\end{center}
+
+In this circuit, the comparator would output a ``1'' if
+
+$$\rm V_{CARD} < V_{TH}-(V_{H}+V_{OFF})$$
+
+and ``0'' if
+
+$$\rm V_{CARD} > V_{TH}+V_{H}+V_{OFF}$$
+
+with
+
+$$\rm V_{CARD} = V_{IO}-(R_{ON}+R_{SHUNT})\cdot (I_{CARD}+I_{CMP})$$
+
+and the following parameters:
+
+\begin{tab}
+\begin{tabular}{l|l}
+ Parameter & Description \\
+ \hline
+ $\rm V_{IO}$ & Supply voltage for SWP\_OUT driver \\
+ $\rm V_{H}$ & Hysteresis (may be zero) \\
+ $\rm V_{OFF}$ & Comparator offset voltage \\
+ $\rm R_{ON}$ & On-state resistance of SWP\_OUT driver \\
+ $\rm R_{SHUNT}$ & Resistance of external shunt resistor \\
+ $\rm I_{CARD}$ & Current drawn by the card's SWIO pin \\
+ $\rm I_{CMP}$ & Input leakage current of the comparator \\
+\end{tabular}
+\end{tab}
+
+To permit reliable detection of S2 states, we therefore need
+$$\rm (R_{ON}+R_{SHUNT})\cdot 580~\mu A \ge 2\cdot (V_{H}+V_{OFF})$$
+where $\rm 580~\mu A$ is the difference between the minimum current at
+S2=1 and the maximum current at S2=0, or
+$$\rm R_{SHUNT} \ge \frac{V_{H}+V_{OFF}}{290~\mu A}-R_{ON}$$
+
+Furthermore, to meet the voltage level requirements from section
+\ref{swpstates}, we need:
+
+$$\rm R_{SHUNT} \le \frac{V_{IO}-1.57~V}{1000~\mu A+I_{CMP}}-R_{ON}$$
+and
+$$\rm R_{SHUNT} \le \frac{0.27~V}{20~\mu A+I_{CMP}}-R_{ON}$$
+
+The DM3730 contains no analog elements and the ADC in the TPS65950
+companion chip has conversion times of tens of microseconds, which
+would be far too slow for \gls{SWP}.\footnote{Table 5-77 in section 5.6.3.1
+of \cite{TPS65950}.}
+
+To implement a detection circuit similar to the above example,
+a comparator external to the CPU would be needed. This could be in
+the form of a dedicated chip or by using a comparator circuit in
+another system component. Section \ref{kl26swp} discusses a possible
+configuration using the built-in comparator of a Kinetis KL26 series
+MCU.
+
+% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+\subsection{SIM card power and card activation}
+
+This section discusses the card activation process, i.e., provisioning
+of power and the communication required before an \gls{SWP} interface can
+be used. We also consider the role of the modem and the consequences
+of sharing a \gls{SIM} card between modem and NFC.
+
+
+\subsubsection{Card activation}
+
+The \gls{SWP} standard defines%
+\footnote{Section 6.2.2 of \cite{SWP}, referring to section 4.5.2.1
+\cite{UICC}, which in turn invokes the procedure defined in section
+6.2 of \cite{ISO7816-3}.}
+card power-up (``activate the contact C1 (Vcc)'') such that
+communication over the SIM's RST (C2), CLK (C3), and I/O (C7)
+pins is required.
+Furthermore, the availability of \gls{SWP} functionality in the card is
+also signaled over the same interface.%
+\footnote{According to section 5.3 of \cite{SWP}, UICC-side support is
+indicated in the ``Global Interface'' bytes in the ATR (Answer to
+reset) defined in section 7 of \cite{ISO7816-3} using the encoding
+from table 6.7 in section 6.3.3 of \cite{UICC}. Terminal-side \gls{SWP}
+capability is communicated at a later point.}
+
+From this it would seem that any \gls{SWP} user must either have the ability
+to communicate with the \gls{SIM} over the regular data interface directly,
+or be able to coordinate \gls{SIM} power-up and capabilities with the
+entity that controls this interface, i.e., the modem.
+
+
+\subsubsection{Role of modem}
+
+Unfortunately, we found no indication in \cite{PHS8P-AT} that the modem
+would allow the host to control \gls{SIM} activation, or that the modem
+would give access to the ATR information (including \gls{SWP} support)
+obtained from the card during activation. There is also no separate
+hardware interface that would allow a 3rd party to request \gls{SIM}
+activation.%
+\footnote{Table 22 in section 6.5 of \cite{PHS8E-HW}.}
+
+Also after activation, the fate of the \gls{SIM} card is uncertain: while
+it seems unlikely that the modem would decide on its own to
+power down the card completely, it can enter clock stop mode with a
+reduced current consumption of 100 $\mu$A.%
+\footnote{Clock stop is defined in section 6.3.2 of \cite{ISO7816-3}
+and the corresponding power consumption is defined in
+sections 5.2.1 (class B) and 5.3.1 (class C) of \cite{UICC}.}
+
+However, this reduced power consumption is only applicable if no
+other interfaces (such as \gls{SWP}) are active. Since the modem has no
+way of knowing whether this is the case, we may have to assume that
+it expects the \gls{SIM} card to adhere to the 100 $\mu$A limit when in
+clock stop mode.
+
+
+\subsubsection{A missed opportunity}
+
+The following drawing summarizes the activation process:
+
+\begin{center}
+\includegraphics[scale=0.9]{simseq.pdf}
+\end{center}
+
+The terminal (modem, etc.) first applies the lowest available voltage
+to the \gls{SIM} card. The card may then send an ATR message on the serial
+interface using CLK and I/O.
+If the terminal receives no message, it switches to the next
+higher voltage, waits again for an ATR message, and so on.
+
+Once ATR has been received, card and terminal can communicate
+some more over the same interface. Once this initial dialog has
+concluded, the \gls{SIM} card is fully operational and the terminal
+can proceed with activating the \gls{SWP} interface.
+
+To do this, it raises the SWIO pin and then waits for a response
+using ACT (ACTivation protocol). If no ACT response arrives, the
+terminal can try to raise the \gls{SIM} card by sending an ACT frame on
+its own, but \cite{SWP} has no provision for negotiating a voltage.%
+\footnote{Section 6.2.3.1 of \cite{SWP}.}
+
+We can conclude from this that the standard clearly expects that any
+user of \gls{SWP} will be able to cooperate closely with the modem when it
+comes to card activation.
+
+
+\subsubsection{Avoiding deactivation}
+
+Section 10.6.4 of \cite{PN544-ODS} describes that the chip is able to
+supply the card with 1.8 V when the phone is deactivated. From the
+available description it is not clear whether this is expected to
+work also in cases where the card has not been previously activated
+through the modem.
+
+Since deactivation by the modem%
+\footnote{Section 6.4 of \cite{ISO7816-3}.}
+requires the removal of power, it should be possible to retain access
+to the \gls{SWP} interface of an activated card indefinitely by ensuring
+that the card's VCC is never allowed to drop.
+
+Note the standard explicitly states that a ``warm reset'' using the
+RST signal\footnote{Section 6.2.3 of \cite{ISO7816-3}.} must not
+affect the state of the \gls{SWP} interface.%
+\footnote{Section 5.4 of \cite{SWP}.}
+
+
+\subsubsection{Power consumption}
+
+The \gls{SIM} card can draw the following maximum current, depending on
+the selected voltage class and power mode:%
+\footnote{Table 6.3 of section 6.2.3 of in \cite{UICC} for full
+ power mode, table 7.1 of section 7.1.2 in \cite{SWP} for low
+ power mode.}
+
+\begin{tab}
+\begin{tabular}{ll|ll}
+ Voltage class & Power mode & Maximum current & Unit \\
+ \hline
+ B & --- & 50 & mA \\
+ C & Full & 30 & mA \\
+ & Low & 5 & mA \\
+\end{tabular}
+\end{tab}
+
+The above applies to current consumption negotiated between card and
+terminal. Table 6.4 in section 6.2.3 of \cite{UICC} also defines a
+minimum current of 10 mA the terminal must be able to supply, which
+seems to be intended to apply irrespective of what current has been
+negotiated.
+
+% -----------------------------------------------------------------------------
+
+\section{NFC chip choices}
+
+We considered the following NFC chips:
+AMS AS3909/3910 \cite{AS3910}
+and AS3911B \cite{AS3911B};
+NXP PN512 \cite{PN512},
+PN532 \cite{PN532-PSDS}, and
+PN544 \cite{PN544-OSDS}; and
+TI TRF7970A \cite{TRF7970A}.
+There are many more NFC chips on the market, but they are less
+known in the developer community and what little documentation
+for them is publicly accessible would be inadequate for an
+evaluation even as superficial as this one.
+
+The chips we consider
+fall into two categories: ``dumb'' chips that implement the radio
+interface and the protocol processing up to the level of frames, and
+``smart'' chips that contain a microcontroller core and that can also perform
+functions of higher protocol layers.
+
+The following table summarizes the roles the chips play in the developer
+community:
+
+\begin{tab}
+\begin{tabular}{l|lllll}
+ Chip & Smart & Documentation & Community \\
+ \hline
+ AMS AS3910 & No & good & unknown \\
+ AMS AS3911B & No & good & unknown \\
+ NXP PN512 & No & good & unknown \\
+ NXP PN532 & Yes & limited & popular \\
+ NXP PN544 & Yes & insufficient & mixed \\
+ TI TRF7970A & No & good & very popular \\
+\end{tabular}
+\end{tab}
+
+One can see that the availability of documentation is inversely
+proportional to the ``intelligence'' of a chip. The PN544 enjoys some
+popularity among software developers, which is probably mainly due to
+the fact that is a often used in NFC-capable smartphones. Unfortunately,
+it is nearly impossible to find any usable information on the hardware.
+The situation is similar but not quite as grim with the PN532, which
+has become a fairly popular choice in the ``maker'' scene.
+
+All the ``dumb'' chips come with good documentation and particularly
+the TRF7970A excels in this regard, with hardware design guides and
+also detailed programming examples for various use cases. While the
+AMS chips and the NXP PN512 seem to be ignored by the Open hardware
+and software scene, the TRF7970A has gathered a certain following.
+
+At the time of writing, the Linux kernel contained drivers for PN532,
+PN544 and TRF7970A.
+
+% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+\subsection{Feature summaries}
+
+The following sections contain summaries of key features that are similar
+in all chips. They are later supplemented with more in-depth discussions
+of the respective chips and their properties.
+
+\def\Y{$\bullet$}
+\def\S{$\circ$}
+\def\N{--}
+\def\M{$\star$}
+
+
+\subsubsection{Cost and availability}
+
+We consulted availability of the chips at major distributors as of
+2014-12-22. Unit prices are in USD for an order of 1000 units.
+If multiple variants of the same chip were available, the price of
+the least expensive was chosen.
+
+\begin{savenotes}
+\begin{tab}
+\begin{tabular}{l|cc|cc|cc}
+ Chip & \multicolumn{2}{c|}{Digi-Key} &
+ \multicolumn{2}{c|}{Mouser} & \multicolumn{2}{c}{Newark}\\
+ & Stock & Price & Stock & Price & Stock & Price\\
+ \hline
+ AS3909-BQTM & \Y & 2.83 & \N & 2.62 & \N & --- \\
+ AS3911B & \N & --- & \N & --- & \N & --- \\
+ PN5120A0HN1/C2,151 & \S & 3.38 & \S & 3.37 & \Y & 3.57 \\
+ PN5321A3HN/C106;55 & \Y & 5.59 & \S & 5.59 & \N & 7.13 \\
+ PN5441A2ET/C20501%
+\footnote{The part number listed by Mouser and Newark does not seem to fit
+ NXP's regular naming scheme. However, the part number could not be
+ verified since \cite{PN544-OSDS} does not include it with the ordering
+ information.}
+ & \N & --- & \N & 4.05 & \N & 5.91 \\
+ TRF7970ARHBR & \Y & 4.31 & \Y & 4.18 & \Y & 4.03 \\
+\end{tabular}
+\end{tab}
+\end{savenotes}
+
+Stock is indicated as \Y\ if there were 1000 or more units stocked,
+\S\ if there less than 1000 but more than zero units (possibly combining
+different forms of presentation, e.g., tape and tray), and ``\N\'' if there
+is no stock. A price of ``---'' means that the part is not listed in the
+catalog.
+
+Note that an older version of the AS3911B exists which is called AS3911-BQFT.
+Despite the ``B'' almost at the right place, this is not the AS3911B.
+The AS3911 is widely available but the AS3911B seems to be too new to have
+reached distributors yet.
+
+
+\subsubsection{Protocol support}
+
+The table below compares support for the various NFC protocols at the
+level of modulation, encoding, and framing. This information is compiled
+from vendor documentation and not based on actual tests. Furthermore,
+some functionality a vendor claims not to support may be available
+through ``raw'' mode.
+
+Capabilities are indicated with the following symbols:
+
+\begin{tab}
+\begin{tabular}{c|l}
+ Symbol & Meaning \\
+ \hline
+ \Y & Supported (according to documentation) \\
+ \S & Support possible via ``raw'' mode \\
+ \N & Not supported \\
+ \M & Supported (\mifare\ extension) \\
+ ? & Documentation ambiguous or insufficient \\
+\end{tabular}
+\end{tab}
+
+For each protocol variant and bit rate, the capabilities are shown for
+the initiator role and the target role (initiator/target). If a capability
+is completely absent, we use --- instead of \N/\N.
+
+\begin{savenotes}
+\begin{tab}
+\begin{tabular}{ccc|cc|ccc|c}
+ Protocol & Variant & kbps &
+\rotatebox{90}{AS3910
+ \footnote{A short overview of features is on page 1 \cite{AS3910}.
+ More details can be found on pages 54--59.
+ Figure 2 on page 2 claims that ISO 15693 and \felica can be implemented
+ using transparent raw mode.}
+ } &
+\rotatebox{90}{AS3911B
+ \footnote{A short overview of features is on page 1 of \cite{AS3911B}.
+ More details can be found on pages 121--135.
+ There is one somewhat enigmatic mention of ISO 15693 on page 136,
+ suggesting that support may be possible in transparent mode.
+ The data sheet never suggests the possibility of the chip operating
+ as \felica\ card or NFC IP-1 passive communication target.}
+ } &
+\rotatebox{90}{PN512
+ \footnote{Capabilities are summarized in sections 2 and 3 of
+ \cite{PN512}. Details can be found in sections 8.1 to 8.4.6.}
+ } &
+\rotatebox{90}{PN532
+ \footnote{Capabilities are summarized in section 1 of \cite{PN532-PSDS}.
+ Details can be found in sections 7.1.3 to 7.1.5.}
+ } &
+\rotatebox{90}{PN544
+ \footnote{Figure 1 on the front page of \cite{PN544-OSDS} gives a nice
+ overview. Details can be found in section 8.}
+ } &
+\rotatebox{90}{TRF7970A
+ \footnote{Most capabilities are described in table 3-1 in section 3 of
+ \cite{TRF7970A}. This table also confusingly mentions that ISO 14443
+ Type A/B at 848 kbps only applies to reader/writer mode.
+ ISO 15693 subcarrier details are in section 6.5,
+ table 6-7. Support for ISO 18000 is also claimed, which probably means
+ Mode 1, equivalent to ISO 15693.
+ Supporting \mifare\ Classic and \mifare\ Ultralight at
+ 106 kbps (via direct mode) is discussed in section 8 of \cite{TRF-FW}.
+ It may be possible to perform Card Emulation also for ISO 15693 using
+ direct mode, see section \ref{rawmode}.}
+ } \\
+ \hline
+ \multirow{8}{*}{ISO 14443} &
+ \multirow{4}{*}{Type A} &
+ 106 & \Y/\N & \Y/\Y & \Y/\Y & \Y/\Y & \Y/\Y & \Y/\Y \\
+ && 212 & \Y/\N & \Y/\N & \Y/\M & \Y/\M & \Y/\Y & \Y/\N \\
+ && 424 & \Y/\N & \Y/\N & \Y/\M & \Y/\M & \Y/\Y & \Y/\N \\
+ && 848 & \Y/\N & \Y/\N & --- & --- & \Y/\Y & \Y/\N \\
+ \cline{2-9}
+ & \multirow{4}{*}{Type B} &
+ 106 & \Y/\N & \Y/? & \Y/? & \Y/? & \Y/\Y & \Y/\Y \\
+ && 212 & \Y/\N & \Y/\N & \Y/? & \Y/? & \Y/\Y & \Y/\N \\
+ && 424 & \Y/\N & \Y/\N & \Y/? & \Y/? & \Y/\Y & \Y/\N \\
+ && 848 & \Y/\N & \Y/\N & --- & --- & \Y/\Y & \Y/\N \\
+ \hline
+ \multicolumn{2}{l}{\multirow{2}{*}{FeliCa}} &
+ 212 & \S/? & \Y/\N & \Y/\Y & \Y/\Y & \Y/\Y & \Y/\Y \\
+ \multicolumn{2}{l}{} &
+ 424 & \S/? & \Y/\N & \Y/\Y & \Y/\Y & \Y/\Y & \Y/\Y \\
+ \hline
+ \multirow{4}{*}{ISO 15693} &
+ \multirow{2}{*}{Single} &
+ 6.62 & \S/? & ?/? & --- & --- & \Y/\N & \Y/? \\
+ && 26.48 & \S/? & ?/? & --- & --- & \Y/\N & \Y/? \\
+ \cline{2-9}
+ & \multirow{2}{*}{Double} &
+ 6.67 & \S/? & ?/? & --- & --- & --- & \Y/\N \\
+ && 26.69 & \S/? & ?/? & --- & --- & --- & \Y/\N \\
+\end{tabular}
+\end{tab}
+\end{savenotes}
+
+NFC IP-1 is not explicitly mentioned here. At 106 kbps it equals
+ISO 14443 Type A, and at higher rates it equals \felica.
+
+
+\subsubsection{Raw mode}
+\label{rawmode}
+
+For a maximum of flexibility, it is desirable to be able
+to bypass the framing mechanisms included in the respective NFC chips
+and to control the radio interface directly from a CPU.
+
+In the transmit direction, the CPU either sends a bit stream that is
+then encoded by the NFC chip and used to modulate the RF field, or
+there can be a pin that leads directly to the transmitter, giving
+the CPU immediate control over modulation. In the receive
+direction, the NFC chip can either perform demodulation, bit decoding
+and clock recovery, and present a clocked bit stream to the CPU, or
+it can just output the demodulated radio signal (without clock) and
+leave all the rest to the CPU.
+
+We call any such mode a ``raw'' mode. AMS call it ``transparent
+mode'', TI call it ``direct mode'', and NXP describe it in terms of
+bypassing elements instead of considering it a proper mode of operation.
+Some chips may also implement
+modes in which basic framing is performed but with relaxed parity or
+CRC checking or similar simplifications.
+
+
+\paragraph{Capabilities}
+
+Chip documentation tends to be somewhat vague on the exact capabilities
+and limitations of raw modes. For example, for the TRF7970A only modes
+corresponding to a reader or initiator role are described,%
+\footnote{Step 3 in the example in section 6.10.6 of \cite{TRF7970A}.}
+i.e., suggesting that load modulation may not be possible in raw mode,
+but discussion on the TI support forum%
+\footnote{NFC/RFID Forum, ``Does TRF7970A support ISO 15693 card emulation?''\\
+ \url{http://e2e.ti.com/support/wireless_connectivity/f/667/t/342797}}
+suggests that it may be possible to perform Card Emulation for
+ISO 15693 using raw mode, which in turn would imply that load modulation
+is supported in raw mode.
+
+Furthermore, the TRF7970A is reportedly capable of acting as a sniffer
+for both initiator and target without configuration changes between
+transmission and reception.%
+\footnote{NFC/RFID Forum, ``NFC Sniffer''\\
+ \url{http://e2e.ti.com/support/wireless_connectivity/f/667/t/330333}}
+
+The TRF7970A also supports a number of ``high-level'' raw modes. They
+are described in more detail in section \ref{tidirect}.
+
+The AS3910%
+\footnote{Page 66 of \cite{AS3910}.}
+appears to only support raw mode in a reader role.
+The AS3911B appears to be considerably more advanced,
+\footnote{Pages 140 to 144 of \cite{AS3911B}.}
+with the same basic functionality as the AS3910 but also a ``stream'' mode
+where encoding and decoding are performed by the AS3911B and data passes
+through the FIFO. The documentation explicitly mentions the use of raw
+mode for future extensions
+of NFC IP-1, non-standard framing of ISO 14443, and \mifare.
+
+The PN512 can be configured to let an external source directly control
+modulation, it gives access to the envelope on the receive side,%
+\footnote{Fields DriverSel and SigOutSel in register RxModeReg in section
+9.2.2.7 of \cite{PN512}.}
+and can output the RF clock as well.%
+\footnote{Field SAMClkD1 in register TestSel1Reg in section 9.2.4.2 of
+\cite{PN512}.}
+It may also be possible to obtain a decoded and clocked bit stream, but
+we did not examine this option in detail.
+
+The PN532 may offer the same functionality in PN512 emulation
+mode (section 2.2 of \cite{PN532-UM}) but it is not clear whether the
+compatibility really goes that deep.
+Available information for the PN544 does not mention any
+``raw'' mode and does not give enough details to determine whether this
+kind of functionality could be implemented using test modes.
+
+
+\paragraph{Digital interface}
+
+The AMS chips reuse the MOSI and MISO pins of the SPI interface for
+modulation and envelope output. The AS3911B can also output a
+phase-demodulated signal on IRQ.%
+\footnote{Page 141 of \cite{AS3911B}.}
+
+PN512 uses dedicated pins SIGIN and SIGOUT for modulation and envelope,
+and D1 to output a clock derived from the carrier frequency.
+The is no corresponding information for PN532 and PN544.
+
+The TRF7970A uses different pins depending on the type of raw mode.
+We examine this in detail in section \ref{trfhost}.
+
+
+\subsubsection{Host interface}
+
+The following table summarizes how the chips connect to the host:
+
+\begin{tab}
+\begin{tabular}{l|llcc}
+ Chip & \multicolumn{2}{c}{Host interface} & 1.8 V & FIFO \\
+ & Regular & Raw mode & & (Bytes) \\
+ \hline
+ AMS AS3910 & SPI & on SPI & \N & 32 \\
+ AMS AS3911B & SPI & SPI, extra & \Y & 96 \\
+ NXP PN512 & SPI, \iic & separate & \Y & 64 \\
+ NXP PN532 & SPI, \iic & ? & \Y & 64 \\
+ NXP PN544 & SPI, \iic & ? & \Y & ? \\
+ TI TRF7970A & SPI & separate & \Y & 127 \\
+\end{tabular}
+\end{tab}
+
+The host interface usually consists of one channel for commands and
+frame data, and one or more channels for bit streams or modulation
+signals in raw modes. These two channels can share the same pins
+(AMS) or they can use a completely different set of pins (NXP and TI).
+
+``1.8 V'' indicates whether the chip can operate with an IO voltage
+of 1.8 V. Note that the main supply voltage is always higher, as shown
+in section \ref{power}.
+
+The FIFO size determines either a) the maximum latency for FIFO
+reads during reception (if the received frame is larger than the FIFO),
+or b) the maximum size a frame can have to be sent or received without
+having to access the FIFO during transmission.
+
+
+\paragraph{SPI sharing}
+
+AMS and TI use the select signal of the SPI interface to signal the end
+of raw mode. They therefore expect that the SPI bus can be assigned to
+NFC use for long periods of time, which may be undesirable if sharing the
+bus with other users.
+
+The PN512 separates the command interface clearly from other uses and
+could therefore share the SPI bus. There is insufficient information
+about PN523 and PN544 to determine whether they have similar characteristics.
+
+
+\paragraph{\iic\ sharing}
+
+Since the PN512 (like all the other NXP NFC chips) has an \iic\ interface,
+one could connect it directly to one of the \iic\ buses of Neo900.
+In the likely event that an MCU is needed for operations with
+tight timing requirements (raw mode, \gls{SWP}, etc.), this would result
+in the two following possible topologies:
+
+\begin{center}
+\includegraphics[scale=0.9]{pn-shared.pdf}
+\hfil
+\includegraphics[scale=0.9]{pn-local.pdf}
+\end{center}
+
+Sharing the same bus for communication between all three parties would
+allow operating the NFC chip from the CPU without involving the MCU at
+all. As a drawback, the MCU would have to switch between master and
+slave roles, and communication between MCU and NFC chip would increase
+occupancy of the \iic\ bus and be subject to its arbitration rules.
+
+The MCU has to relay all communication between CPU and NFC chip
+if a dedicated \iic\ or SPI bus is used between MCU and NFC.%
+\footnote{This would require some amount of customization in the bottom
+ end of the (kernel) driver, but we can expect some work of this sort
+ to be needed no matter how the NFC chip is connected to the main CPU.
+ In any case, the driver would benefit from being able to delegate
+ low-level tasks like the timely handling of the FIFO to the MCU.}
+
+
+\subsubsection{Power consumption}
+\label{power}
+
+The following table summarizes the supply voltage ranges of the various
+chips, and their current consumption in typical operation states.
+``Off'' is the lowest power state the chip can be commanded to enter.
+``Field detect'' is a low-power state from which the chip can awaken
+when it enters the field of an active reader. ``Idle'' is a typical
+state where the chip is operational but not actively communicating.
+``Transmit'' is when it is transmitting with maximum power.
+
+\begin{savenotes}
+\begin{tab}
+\begin{tabular}{l|cc|ccccccc}
+ Chip & \multicolumn{2}{c|}{Voltage}
+ & \multicolumn{7}{c}{Current} \\
+ & $\rm V_{IN}$ & $\rm V_{IO}$
+ & \multicolumn{2}{c}{Off}
+ & \multicolumn{2}{c}{Field detect}
+ & \multicolumn{2}{c}{Idle} & Transmit \\
+ \hline
+ Unit & V & V
+ & \multicolumn{2}{c}{$\mu$A}
+ & \multicolumn{2}{c}{$\mu$A}
+ & \multicolumn{2}{c}{mA} & mA \\
+ & & & Typ & Max & Typ & Max & Typ & Max & Max \\
+ \hline
+ AS3909
+\footnote{Single supply voltage from figure 7 on page 7 of \cite{AS3910},
+ all other parameters from figure 9 on page 8.}
+ & 2.4--3.6 & $\rm V_{IN}$
+ & 0.3 & 2 & 3.5 & 7 & 2 & 3 & ? \\
+ AS3911B
+\footnote{$\rm V_{IN}$ and $\rm V_{IO}$ from figure 6 on page 8 of
+ \cite{AS3911B}, maximum transmit power from figure 5 on page 6,
+ all other parameters from figure 9 on pages 9 and 10.}
+ & 2.4--5.5 & 1.65--5.5
+ & 0.7 & 2 & 3.5 & 7 & 5.4 & 7.5 & 500 \\
+ PN512
+\footnote{$\rm V_{IN}$ and $\rm V_{IO}$ from table 1 in section 4 of
+ \cite{PN512}, all other parameters from table 169 in section 26.
+ Idle and transmit current are sums across several supply inputs.}
+ & 2.5--3.6 & 1.6--3.6
+ & -- & 5 & -- & 10 & 9.5 & 19 & 114 \\
+ PN532
+\footnote{All parameters are from table 1 in section 4 of \cite{PN532-PSDS}.
+ Maximum transmit current is the sum of several supply inputs.}
+ & 2.7--5.5 & 1.6--3.6
+ & -- & 2 & -- & 45 & 25 & -- & 186 \\
+ PN544
+\footnote{All parameters are from table 1 in section 4 of \cite{PN544-OSDS}.}
+ & 2.3--5.5 & 1.6--3.3
+ & 5 & -- & 10 & -- & ? & -- & 100 \\
+ TRF7970A
+\footnote{$\rm V_{IO}$ according to table 4.1 in section 4.2 of
+ \cite{TRF7970A}, section 6.1.3 for current with field detection,
+ section 5.2 for $\rm V_{IN}$, and section 5.3 for all other parameters.}
+ & 2.5--5.5 & 1.8--$\rm V_{IN}$
+ & 0.5 & 5.0 & 3.5 & ? & 1.9 & 3.5 & 150 \\
+\end{tabular}
+\end{tab}
+\end{savenotes}
+
+Of these chips, only the PN532 and PN544 support field-powered operation.
+
+
+\subsubsection{Antenna interface}
+
+The various chips all have low-impedance outputs and require external
+components for antenna matching and for mixing the TX and RX signals.
+
+\begin{savenotes}
+\begin{tab}
+\begin{tabular}{l|cc|ccc|c}
+ Chip & \multicolumn{2}{c|}{Impedance} & \multicolumn{3}{c|}{Example circuit}
+ & $50~\Omega$ port \\
+ & TX & RX & L & C & R & \\
+ \hline
+ AS3910
+ \footnote{Impedances in figure 9 on page 8 of \cite{AS3910}, example
+ circuit (without component values) in figure 10 on page 10.}
+ & $1.5~\Omega$ & $10~{\rm k}\Omega$ & -- & 4 & 1 & No \\
+ AS3911B
+ \footnote{Impedances in figure 9 on page 11 of \cite{AS3911B}, example
+ circuit (without component values) in figure 10 on page 12.
+ A more complex example circuit with component values, similar
+ to the one in figure 11 can be found on page 7 of
+ \cite{AS3911-DOOR}.}
+ & $0.6~\Omega$ & $10~{\rm k}\Omega$ & 1 & 5 & 1 & No \\
+% driver output resistance == impedance ?
+ PN512
+ \footnote{Impedance in table 169 in section 25 of \cite{PN512},
+ example circuit (without component values) in figure 38, section
+ 22.
+ Antenna matching is described in much more depth in excellent
+ \cite{PN512-ANT}.}
+ & $3~\Omega$ & $350~\Omega$ & 2 & 8 & 4 & No \\
+ PN532
+ \footnote{Impedance is not specified in available documentation,
+ but we may assume it to be equivalent to the PN512.
+ Example circuit in figure 13, section 9 of \cite{PN532-PSDS}. Note
+ that load modulation can be achieved without the additional
+ circuit on pin LOADMOD. \cite{PN512-ANT} also applies to the
+ PN532.}
+ & ? & ? & 2 & 8 & 4 & No \\
+ PN544
+ \footnote{Impedance is not specified in available documentation.
+ Example circuit in figures 13 and 14, section 12 of \cite{PN544-OSDS}.
+ The component count is for the design variant not supporting
+ field-powered operation.}
+ & ? & ? & 2 & 6+1 & 6 & No \\
+ TRF7970A%
+ \footnote{Impedance in section 7.4 of \cite{TRF7970A}, example circuit
+ in figure 7-1 in section 7.1.2, antenna matching in \cite{TRF-ANT}.}
+ & $4~\Omega$ & $10~{\rm k}\Omega$ & 2 & 13 & 1 & Yes \\
+\end{tabular}
+\end{tab}
+\end{savenotes}
+
+The component counts omit items that have no effect (DNP, $0~\Omega$, etc.)
+
+All designs based on the TRF7970A and its predecessor the TRF7960 the
+author could find included a $50~\Omega$ port in the path towards the
+antenna, with the corresponding impedance matching. It may therefore
+be possible to achieve some simplification by omitting this port. The
+designs by AMS and NXP do not include such ports.
+
+% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+\subsection{AMS AS3909/3910}
+
+The AS3909%
+\footnote{\url{https://www.ams.com/eng/Products/NFC-HF-RFID/NFC-HF-RFID-Reader-ICs/AS3909}}
+is a very basic NFC chip mainly designed for readers.
+The AS3910%
+\footnote{\url{https://www.ams.com/eng/Products/NFC-HF-RFID/NFC-HF-RFID-Reader-ICs/AS3910}}
+is very similar except that it contains advanced antenna tuning
+capabilities.
+
+The limited radio capabilities, the 3.3 V host interface, and the
+apparent lack of support in the developer community make these chips
+unattractive for our purposes.
+
+% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+\subsection{AMS AS3911B}
+
+The AS3911B%
+\footnote{\url{https://www.ams.com/eng/Products/NFC-HF-RFID/NFC-HF-RFID-Reader-ICs/AS3911B}}
+is a chip that is designed mainly for a reader role, but it can
+also support some modes commonly found in smartphones. As the only
+chip in this comparison, it expressly supports EMV \cite{EMV}. At
+least at the lower protocol layers, EMV seems to be merely another
+rehash of ISO 14443 Type A and B.
+
+All things
+considered, this is still a very limited chip, it seems to be unknown
+in the developer community, and the lack of availability of the ``B''
+version may be an issue.
+
+% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+\subsection{NXP PN512}
+
+The PN512%
+\footnote{\url{http://www.nxp.com/products/identification_and_security/nfc_and_reader_ics/nfc_contactless_reader_ics/PN512AA0HN1.html}}
+looks somewhat promising. It supports ISO 14443 and NFC IP-1 in both
+initiator and target roles, fairly detailed documentation is available,
+and interfacing should be reasonably simple (for raw modes, using a
+microcontroller synchronized to the carrier frequency).
+
+Drawbacks of this chip include the apparent lack of community interest,
+the lack of support for ISO 15693, and also the limitation to lower
+bit rates.
+
+% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+\subsection{NXP PN532}
+
+The PN532%
+\footnote{\url{http://www.nxp.com/products/identification_and_security/nfc_and_reader_ics/nfc_contactless_reader_ics/PN5321A3HN.html}}
+enjoys great popularity in the DIY hardware scene.
+
+A driver for the PN533, which should be identical except for the interface,
+is included in the mainline Linux kernel ({\tt drivers/nfc/pn533.c}).
+
+Documentation may be a problem, though. At least the publicly available
+documentation is insufficient for considering this chip.
+It also seems to share the low-level protocol support weaknesses of the PN512.
+
+% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+\subsection{NXP PN544}
+
+The PN544 is very popular in the industry and can be found in many
+smartphones. Low-level protocol support is quite comprehensive and
+among the chips we considered, this is the only one with a built-in
+\gls{SWP} interface.
+
+Unfortunately, almost no public documentation is available
+for the chip.
+There are a ``3rd generation'' successor chip,%
+\footnote{\url{http://www.nxp.com/products/identification_and_security/nfc_and_reader_ics/nfc_contactless_reader_ics/series/PN547.html}}
+the PN547, announced in 2012, and the ``4th generation'' PN548 that are
+even more elusive.
+
+A driver for the PN544 is included in the mainline Linux kernel
+({\tt drivers/nfc/pn544/}).
+
+Given the extremely poor documentation situation, we should not consider
+this chip suitable for use in the Neo900 project.
+
+% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+\subsection{TI TRF7970A}
+
+The TRF7970A%
+\footnote{\url{http://www.ti.com/product/trf7970A}}
+is readily available, comes with comprehensive documentation, and
+considerable design experience exists in the community.
+
+It is much simpler than the NXP PN544, covering
+only the lower layers of the NFC/RFID protocol stack. This puts a
+larger burden on the host but also ensures a maximum of flexibility
+and allows to omit functionality that would create ``intellectual
+property'' liabilities.
+
+Possible issues include that the chip has a comparably complex
+host interface that is based on SPI, not \iic, and that it does not
+include \gls{SWP} support.
+
+A vendor-supported driver for the TRF7970A is included in the
+mainline Linux kernel\linebreak ({\tt drivers/nfc/trf7970a.c}).
+
+
+\subsubsection{Non-standard protocols}
+\label{tidirect}
+
+For transceiver configuration and when using protocols whose framing
+complies with the ISO 14443 standard,%
+\footnote{Section 6.2.3 of \cite{ISO14443-3}}
+communication with the host CPU uses
+an SPI interface plus one signal each for enabling the chip and for
+signaling interrupts to the host.
+
+If using protocols that do not comply with ISO 14443-3 framing but use
+a similar structure,%
+\footnote{According to \cite{MIFARE-Classic}, \mifare\ Classic complies
+ with ISO14443-1 through ISO14443-3 but violates ISO14443-4, while
+ \cite{TRF-FW} suggests that already the framing does not correspond
+ to ISO14443-3.}
+a so-called ``Special Direct Mode'' (SDM, sometimes
+also called DM2) has to be
+used. For receiving, this mode uses the same interface as for
+standard-compliant communication.
+When sending, the CPU enables the transmitter with the special enable
+signal (TX\_EN), the transceiver provides the bit clock, and the host sends the
+bit stream to transmit.
+
+Last but not least, if the protocol diverges even further from the standard,
+one of two additional ``Direct Modes'' (DM) have to be used. For
+transmission, the host provides the modulation signal (i.e., below the bit
+level).
+
+Both direct modes differ for reception: DM1 performs demodulation and
+decoding
+of received bits, and provides bit clock and bitstream to the host. In DM0,
+the transceiver outputs the digitized envelope signal.
+
+The following diagram illustrates where the various direct modes tap into
+the data flow between the protocol processing layers:
+
+\begin{center}
+\includegraphics[scale=0.9]{trf-stack.pdf}
+\end{center}
+
+Further details on DM0 and DM1 can be found in section 6.10.6 of
+\cite{TRF7970A}. SDM is discussed in section 8 of \cite{TRF-FW}.
+
+
+\subsubsection{Modulation clock}
+\label{trfclk}
+
+In DM0 and DM1, the host has to provide modulation input that is
+synchronized precisely with the carrier frequency.
+
+The carrier frequency of ISO 14443-2 is 13.56 MHz $\pm$ 7 kHz
+and all other timings are derived from this frequency.%
+\footnote{Section 6.1 of \cite{ISO14443-2}.}
+At the lowest specified nominal
+rate of 106 kHz (\fcfrac{128}), the bit clock would therefore be between
+105.88 kHz and 105.99 kHz.
+Modulation inside bits uses a multiple of the bit rate but also allows
+for considerably larger tolerances.
+
+To help the host to meet clocking requirements of the RF side, the
+transceiver can output a clock directly derived from the carrier clock.
+The SPI modules in the DM3730 operate at an integer fraction of a
+48 MHz clock and cannot be clocked from any other source in master
+mode.
+
+Type A modulation at \fcfrac{128} requires a pulse $t_1$ of \fracfc{28}
+to \fracfc{40.5}
+that starts with an exact delay of zero or half the bit period ($t_x=64/\fc$)
+after the nominal beginning of a bit.%
+\footnote{Table 3 in section 8.1.2.1 and table 7 in section 8.1.3
+of \cite{ISO14443-2}.}
+Taking into account carrier
+frequency tolerances, we therefore obtain the following timings for
+the beginning of the $t_1$ pulse:
+
+\begin{tab}
+\begin{tabular}{c|c}
+ Time ($\mu s$) & 48 MHz cycles \\
+ \hline
+ 4.7173--4.7222 & 226.43--226.67 \\
+\end{tabular}
+\end{tab}
+
+It is therefore not possible to provide accurate $t_x$ timing with
+the SPI subsystem of the DM3730 operating as master.
+
+If used as slave, the DM3730's SPI interfaces can operate at 12 MHz in
+OPP50 and at 24 MHz in OPP100. The -- possibly divided -- RF clock could
+therefore be used as SPI bus clock for transmission in DM0 and DM1,
+and also for reception in DM0.
+
+Unfortunately, the DM3730 has the unusual requirement that the SPI
+select signal has to raise at the end of each word, and is therefore
+not suitable for receiving a continuous bit stream.%
+\footnote{Section 20.5.3 in \cite{DM3730-TRM}.}
+
+This issue can be resolved in the following manners:
+\begin{itemize}
+ \item Support only standard-compliant protocols, without any of the
+ direct modes,
+ \item implement non-standard protocols with DM0 (DM1 reception and
+ SDM are unavailable due to the requirement to de-select the DM3730
+ SPI slave between bytes), using an SPI master with an
+ out-of-specification data clock derived from the 48 MHz source,
+ \item try to generate the bit stream entirely under software control,%
+\footnote{Since very narrow timing is required, such a program would have
+ to disable interrupts,
+ suppress or compensate for conflicting bus activity (e.g., DMA transfers),
+ ensure a known and stable cache state, and may have to take additional
+ precautions to keep jitter to a minimum. In practice, the CPU would be
+ dedicated to executing only the code in question during communication
+ preparation and the actual communication. This is likely to result in
+ user-visible effects and the impact large interrupt handling delays have
+ on drivers would have to be analyzed.}
+ \item use a different transceiver, or
+ \item add a microcontroller capable of relaying data between DM3730
+ and TRF7970A. An example for this approach is shown in section
+ \ref{kl26}.
+\end{itemize}
+
+Support of type B modulation and the optional%
+\footnote{Table 1 in section 6.1 of \cite{ISO14443-3}}
+bit rates above 106 kHz was not studied for this document.
+
+
+\subsubsection{Host interface}
+\label{trfhost}
+
+In this section we describe connections between the transceiver and the
+host CPU for the various transmission modes.
+
+The simplest case is standard-compliant operation using framing and
+FIFO:
+
+\begin{center}
+\includegraphics[scale=0.9]{trf-std.pdf}
+\end{center}
+
+The transceiver operates as a SPI slave and the SPI bus can be shared
+with other devices.
+
+For ``Special Direct Mode'', reception still uses the transceiver's
+internal FIFO and SPI, but transmit enable, data, and clock use dedicated
+signals:
+
+\begin{center}
+\includegraphics[scale=0.9]{trf-sdm.pdf}
+\end{center}
+
+Furthermore, the interface must remain selected. If the SPI bus is
+shared with other devices, it must therefore be held until the
+send or receive operation -- or sequence of operations -- is complete.
+
+It is not clear whether the SPI interface can be used during SDM
+transmission or whether DATA\_CLK has to remain idle.
+
+In DM1, the receiver uses the signals of the SPI interface for
+demodulated bits and the bit clock:
+
+\begin{center}
+\includegraphics[scale=0.9]{trf-dm1-rx.pdf}
+\end{center}
+
+As in SDM, nSS has to be held low while using either DM0 or DM1.
+The documentation is inconsistent as to whether interrupts may be
+generated in DM1.
+
+In DM0, the receiver delivers only the ``raw'' envelope without
+clock (DM0). Transmission in DM0 and DM1 uses yet another data path
+for the modulation signal. Since DM0 reception and DM0/DM1 transmission
+need to be tightly synchronized with the RF carrier frequency, we use
+the transceiver's clock output to clock the SPI bus, as discussed in
+section \ref{trfclk}:
+
+\begin{center}
+\includegraphics[scale=0.9]{trf-dm-sysclk.pdf}
+\end{center}
+
+The OOK control signal allows the host to change ``on the fly''
+between \gls{OOK} or \gls{ASK}. It is presently
+not clear under what circumstances such functionality would be required.
+
+Since it appears that at most one data stream (i.e., SPI, TX/RX bits,
+or modulation/envelope information) is active at any given time, it
+should be possible to operate the transceiver with a single SPI interface
+from the host. The circuit for this may look as follows:
+
+\begin{center}
+\includegraphics[scale=0.9]{trf-comb.pdf}
+\end{center}
+
+Note that IO\_5 is an active if useless output also in SPI mode and
+therefore must be separated from SPI clock generated by the host.
+The following table shows the different clock configurations:
+
+\begin{tab}
+\begin{tabular} {l|l|ll}
+ Protocol mode & SPI mode & \multicolumn{2}{c}{Clock mode} \\
+ & & Clock selection & DATA\_CLK \\
+ \hline
+ Standard, SDM RX & Master & SPI & SCLK \\
+ SDM TX, DM1 RX & Slave & TRX & L \\
+ DM0, DM1 TX & Slave & RF & L \\
+\end{tabular}
+\end{tab}
+
+Note that IO\_2 must be held high on ``power-up'' (which seems to
+include EN transitioning from low to high)
+to select the four-wire SPI interface configuration.
+
+
+\subsubsection{Activity states}
+
+The TRF7970A has two enable lines that allow the selection of up to
+three different activity states:%
+\footnote{Table 6-3 in section 6.3.2 of \cite{TRF7970A}.}
+
+\begin{tab}
+\begin{tabular}{l|cc|ll}
+ State & EN & EN2 & SYS\_CLK & $\hbox{V}_{\rm DD\_X}$ \\
+ \hline
+ Power down & 0 & 0 & off & off \\
+ Sleep & 0 & 1 & off & on \\
+ All others & 1 & X & on & on \\
+\end{tabular}
+\end{tab}
+
+SYS\_CLK is the clock output and $\hbox{V}_{\rm DD\_X}$ is a regulated
+voltage derived from the 3.3 V input supply. Since we need neither when
+in a standby state, it is not necessary to use EN2 and we can connect
+it permanently to ground.
+
+According to sections 6.1.3 and 6.12.1 of \cite{TRF7970A}, field detection
+is supplied by ``VEXT'' and is therefore possible also ``during complete
+power down.'' Unfortunately, there is no power supply with this name.
+
+The description of table 6-15 in section 6.12.1 suggests that the
+mysterious ``VEXT'' may be identical to ``$\hbox{V}_{\rm IN}$''.
+
+% -----------------------------------------------------------------------------
+
+\section{Auxiliary microcontroller}
+\label{kl26}
+
+In this section we describe a possible scenario where an auxiliary
+microcontroller is used to implement SWP, and to overcome the incompatibility
+between the
+capabilities the TRF7970A requires from a host CPU in order to support
+non-standard protocols and what the DM3730 provides. In this example,
+we use the Freescale Kinetis L series KL26 in a 32-QFN package.
+
+The KL26 was chosen in part because of the author's familiarity with
+this chip. The Kinetis L series contains many other chips with similar
+characteristics that -- pending further evaluation -- could be
+used in its stead. For example, if we have no use for the USB
+functionality, the otherwise similar KL16 would have more available
+IO pins and a slightly lower unit cost.
+
+% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+\subsection{Host interface}
+
+This section describes the signals between the MCU (KL26) and the
+host CPU (DM3730).
+
+The KL26 contains two \iic\ modules which are both capable of operating
+at 1.8 V and at 400 kbps, provided that the \iic\ bus is connected to
+one of the chip's high-drive pads.%
+\footnote{Footnote 1 below table 35 in section 3.8.4 of \cite{KL26}.
+See also table 7 in section 2.2.3 for high-drive pads, and
+section 5.1 for pin assignment. Note that only I2C0 is actually routed
+to high-drive pads.}
+
+An \iic\ address match can wake the chip from various low-power modes.%
+\footnote{Table 7-2 in section 7.5 of \cite{KL26RM}.} Of these modes,
+VLPS it the one with the lowest power consumption, with a typical
+2.69 $\mu$A at \degree{25}.\footnote{Table 9 in section 2.2.5 of \cite{KL26}.}
+
+Additional signals to the host are a reset signal to unconditionally
+reset the MCU, and an interrupt signal to alert the host to NFC
+activity.
+
+Furthermore,
+the SWD signal used for in-circuit programming may or may not be routed
+to the host CPU. See section \ref{kl26prog} for details.
+
+% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+\subsection{Clock configuration}
+
+In order to perform all the clock selection inside the chip, without
+requiring any external components,
+we clock the KL26 from the transceiver.%
+\footnote{The KL26 contains an USB OTG interface that requires a 48 MHz
+clock that could not be derived with sufficient accuracy from the NFC
+clock. However, if use of USB is required while processing non-standard
+NFC protocols, it may still be possible to use the internal FLL clock
+for this purpose. Given the complexity of the MCU's clocking system,
+the viability of this configuration should not be taken for granted
+without verification by experiment.}
+In this scenario, the following clock configuration could be used:%
+\footnote{In this example, we assume that the transceiver outputs \fc.
+The TRF7970A could also output a fractional clock or, if using a
+27.12~MHz crystal (which may be more easily available than 13.56~MHz),
+it could output twice \fc. The input divider of the PLL can be adjusted
+to any of these frequencies.}
+
+\begin{tab}
+\begin{tabular}{lclclcl}
+Clock & & Input clock & & Divider & & Frequency (MHz) \\
+
+\hline
+EXTAL0 & = & 13.56 MHz & $\div$ & 4 & = & 3.39 \\
+\hline
+PLL input & = & EXTAL0 & $\div$ & 1 & = & 3.39 \\
+PLL output & = & PLL input & $\times$ & 24 & = & 81.36 \\
+System & = & PLL output & $\div$ & 2 & = & 40.68 \\
+Bus & = & System & $\div$ & 2 & = & 20.34 \\
+\end{tabular}
+\end{tab}
+
+The PLL output is limited to 100 MHz, the system clock to 48 MHz,
+and the bus clock to 24 MHz. The above settings therefore run the
+KL26 at 84.75\% of its maximum speed.
+
+% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+\subsection{SPI configuration}
+
+The KL26 has two SPI interfaces that are both capable of operating
+in master and slave mode. The maximum speed of each SPI interface
+depends on the (hard-wired) clock source and in which mode it
+operates. With the above clock configuration, we would obtain the
+following maximum bit rates:
+
+\begin{tab}
+\begin{tabular}{llll}
+SPI device & Mode & Highest rate & MHz \\
+\hline
+SPI0 & Master & $f_{\rm BUS}/2$ & 10.17 \\
+ & Slave & $f_{\rm BUS}/4$ & ~5.08 \\
+SPI1 & Master & $f_{\rm SYS}/2$ & 20.34 \\
+ & Slave & $f_{\rm SYS}/4$ & 10.17 \\
+\end{tabular}
+\end{tab}
+
+We should therefore use SPI0 as SPI master for transceiver configuration
+and the transfer of standard-compliant frames, and SPI1 for all the
+direct modes, either as
+master with a maximum
+SPI bit clock of $\rm\sfrac{20.34~MHz}{3}=6.78~MHz=\fcfrac{2}$,
+or as slave.
+
+Note that there is probably a complication in the form of a delay of
+half a bit time between bytes when operating as SPI master.%
+\footnote{``KL15 - DMA with SPI - Interbyte delay'' \\
+ \url{https://community.freescale.com/thread/308798}}
+Possible alternatives to SPI would include \iis, which has a continuous
+clock, is also available in the chips discussed here, and
+should be able to operate at data rates up to 12.5 MHz,
+or a fairly generic serial protocol engine called FlexIO \cite{AN4955}
+that has recently been introduced in some Freescale microcontrollers.
+
+% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+\subsection{Connection example}
+
+The following drawing shows a possible wiring of the interface between
+TRF7970A and KL26:
+
+\begin{center}
+\includegraphics[scale=0.9]{trf-kl26.pdf}
+\end{center}
+
+Note that no external switches or multiplexers are required.
+As explained in
+section 3.1 of \cite{TRF-POWER-DOWN}, inputs that are driven high while
+the chip is not enabled draw a significant idle current. To avoid this,
+IO\_1 should be connected to a GPIO and only be driven high when needed
+for interface selection, and the SPI bus should not be
+shared with other devices.
+
+The following table shows which of the connections would be used to
+carry data and clock in each transceiver mode, and which signal
+activates the SPI slave:
+
+\def\la{$\leftarrow$}
+\def\ra{$\rightarrow$}
+
+\begin{tab}
+\begin{tabular}{lc|ccc}
+Mode & Direction & Data & Clock & Select \\
+ & & NFC $\leftrightarrow$ MCU
+ & NFC $\leftrightarrow$ MCU
+ & NFC $\leftrightarrow$ MCU \\
+\hline
+Standard & TX & \la MOSI & \la SCLK & \la nSS \\
+ & RX & MISO\ra & \la SCLK & \la nSS \\
+SDM & TX & \la TXD & TRX\_CLK\ra & --- \\
+ & RX & MISO\ra & \la SCLK & \la nSS \\
+DM1 & RX & RXD\ra & TRX\_CLK\ra & SELF\ra \\
+DM0, DM1 & TX & \la MOD & NFC\_CLK\ra & --- \\
+DM0 & RX & RXD\ra & NFC\_CLK\ra & SELF\ra \\
+\end{tabular}
+\end{tab}
+
+% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+\subsection{SWP interface example}
+\label{kl26swp}
+
+The Kinetis KL26 family includes a fast analog comparator with
+built-in programmable voltage references. This can be used to implement
+an \gls{SWP} interface as described in section \ref{swpcmp}.
+
+Since we need to be able to sample the S2 state within an interval
+of 1.25 $\mu$s or shorter, we assume that the comparator is operated in
+high-speed mode with a maximum propagation delay of 200 ns.%
+\footnote{Table 27 in section 3.6.2 of \cite{KL26}.}
+
+We can obtain the following parameters from the data sheet \cite{KL26}:
+\begin{tab}
+\begin{tabular}{l|lccl}
+ Parameter & Reference, section & Value & Unit & Comment \\
+ \hline
+ $\rm V_{H}$ & Figure 10, 3.6.2 & 5--160 & mV &
+ Typical, configurable, near rail \\
+ $\rm V_{OFF}$ & Table 27, 3.6.2 & 20 & mV & Maximum \\
+ $\rm I_{CMP}$ & Table 7, 2.2.3 & 1 & $\mu$A & Maximum \\
+ $\rm R_{ON}$ & Table 7, 2.2.3 & 200 &
+ $\Omega$ & Normal drive pad, maximum \\
+ & & 50 &
+ $\Omega$ & High drive pad, maximum \\
+\end{tabular}
+\end{tab}
+
+Assuming the use of a high-drive pad to minimize the effect of
+$\rm R_{ON}$ variations, the minimum hysteresis of $\rm V_{H}=5~mV$,
+and $\rm V_{IO}=1.8~V$,
+we obtain the following
+constraints for $R_{SHUNT}$ using the formulas from section \ref{swpcmp}:
+
+
+%===== fp block =====
+
+% Fixed device characteristics:
+
+\FPeval{voff}{.02} % Voff = 20 mV
+\FPeval{icmp}{0.0000001} % Icmp = 1 uA
+
+% Parameters we choose:
+
+\FPeval{ron}{50} % Ron = 50 Ohm
+\FPeval{vh}{0.005} % Vh = 5 mV
+\FPeval{vio}{1.8} % Vio = 1.8 V
+
+% From swdcmp:
+
+\FPeval{rshmin}{(vh+voff)/0.000290-ron}
+\FPeval{rshmax}{(vio-1.57)/(0.001+icmp)-ron}
+
+%====================
+
+
+$$\rm \FPrnd{1}{rshmin}~\Omega \le R_{SHUNT}
+ \le \FPrnd{0}{rshmax}~\Omega$$
+
+If we choose $R_{SHUNT}=150~\Omega$, $\rm V_{CARD}$ and $\rm V_{TH}$ for the
+S2 states then are:
+
+
+%===== fp block =====
+
+% Parameters we choose:
+
+\FPeval{rshunt}{150} % Rshunt = 150 Ohm
+
+% Function to calculate Vcard and Vth from Icard (and global settings) and
+% offset (Vh+Voff) multiplier:
+
+\def\fvcard#1#2{\FPrnd{3}{(vio-(ron+rshunt)*((#1)+icmp))+(#2)*(vh+voff)}}
+
+%====================
+
+
+\begin{tab}
+\begin{tabular}{ll|cc}
+ S2 & $\rm I_{CARD}$ & $\rm V_{CARD}$ & $\rm V_{TH}$ \\
+ \hline
+ 1 & 600 $\mu$A (min) & \fvcard{.0006}{0} V & \fvcard{.0006}{1} V (min) \\
+ 0 & 20 $\mu$A (max) & \fvcard{0.00002}{0} V & \fvcard{0.00002}{-1} V (max)\\
+\end{tabular}
+\end{tab}
+
+The analog comparator in KL26 has a 6-bit DAC that can be used as
+power-efficient voltage reference. Considering DAC non-linearity,%
+\footnote{$\rm\pm 0.8~LSB$ with $\rm 1~LSB=\rfrac{1}{64}~V_{IO}$,
+table 27 in section 3.6.2 of \cite{KL26}.}
+the following DAC setting%
+\footnote{Section 29.2.5 of \cite{KL26RM}. Note that the divider is indeed
+64 (and not 63) because the DAC range is
+from $\rm \rfrac{1}{64}\cdot V_{IO}$ to $\rm \rfrac{64}{64}\cdot V_{IO}$
+and thus does not include GND.}
+would produce a voltage in the above range:
+
+
+%===== fp block =====
+
+% Fixed device characteristics:
+
+\FPeval{vcmperr}{1.8/64*(0.5+0.3)} % LSB*(INL+DNL)
+
+% Parameters we choose:
+
+\FPeval{dacvosel}{62}
+
+% Function to calculate Vdaco from dacvosel and error multiplier:
+
+\def\vdaco#1{\FPrnd{3}{vio/64*dacvosel+(#1)*vcmperr}}
+
+%====================
+
+
+\begin{tab}
+\begin{tabular}{l|ccc}
+ $\rm \times V_{IO}$ & \multicolumn{3}{c}{Voltage (V)} \\
+ & Min. & Nom. & Max. \\
+ \hline
+% \rfrac{61}{64} & 1.693 & 1.739 \\
+ $\rfrac{\strut \FPfmt{dacvosel}}{64}$ & \vdaco{-1} & \vdaco{0} & \vdaco{1} \\
+% \rfrac{63}{64} & 1.749 & 1.795 \\
+\end{tabular}
+\end{tab}
+
+Please note that we may choose less rigid requirements for $\rm V_{CARD}$,
+as discussed in section \ref{swpcmp}. This would allow the use of a larger
+shunt resistance, allowing for a larger hysteresis and/or a wider threshold
+voltage range.
+
+% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+\subsection{Pin assignment}
+
+The following drawing shows a possible pin assignment for the KL26
+operating at 1.8 V, with a simple \iic-based interface to the main CPU:
+
+% Should be scale=0.9. Shrinked to fit on page.
+\begin{center}
+\includegraphics[scale=0.87]{kl26-32.pdf}
+\end{center}
+
+The pin descriptions only list functions pertinent to a possible use in
+Neo900. The KL26 makes extensive use of multiplexing and most pins have
+between four and six different functions.
+
+% Note that it would be possible to assign TXD and MOD (which can
+% be bi-directional, but apparently only in receive situations, i.e.,
+% when TXD would not be used) to separate pins if desired.
+%
+SWP\_S1 connects to pin 31 (PTD6), which is a high-drive pad, as suggested
+in section \ref{kl26swp}. High-drive pads are marked with a grey bar.
+
+% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+\subsection{In-circuit programming}
+\label{kl26prog}
+
+The KL26's internal Flash memory can be in-circuit programmed through
+the SWD interface. To avoid conflicts with other parts of the system,
+the SWD signals should either be used exclusively for SWD, or -- if
+sharing is desired -- should connect to high-impedance inputs that do
+not normally trigger major transitions in system state.
+
+Like apparently all microcontrollers of this category, the KL26 can
+be programmed to disallow any direct outside access to its Flash content.
+Firmware present in Flash may allow indirect read or write access to the
+Flash.
+This effectively means that the chip can be irreversibly ``bricked''
+by flashing an incorrect firmware image. In the context of Neo900,
+this ability would be highly undesirable.
+
+The SWD programming software could be equipped with safeguards that
+prevent the flashing of content that would lead to such bricking.
+However, a bug, a communication error, or also malicious software
+could still defeat such a mechanism.
+
+A safe choice would be to program an \iic-based boot loader into the
+MCU. This boot loader would run after reset, accept possible changes
+to the rest of the firmware, and only proceed to normal operation
+when requested by the main CPU. That boot loader itself would be
+protected against alteration.
+
+Modification of the boot loader in the field could be permitted
+either through the boot loader's \iic\ protocol, via SWD, or both.
+In either case, a suitable safeguard against unintended programming
+should be provided, e.g., by requiring the placement of a jumper.
+
+% -----------------------------------------------------------------------------
+
+\setglossarystyle{long}
+\setlength{\glsdescwidth}{14cm}
+\glsnogroupskiptrue
+\printglossary[type=\acronymtype,title=Acronyms and abbreviations]
+
+% -----------------------------------------------------------------------------
+
+\clearpage
+\begin{thebibliography}{28}
+\input nfc.bbl
+\end{thebibliography}
+
+\end{document}
diff --git a/nfc/pn-local.fig b/nfc/pn-local.fig
new file mode 100644
index 0000000..273f782
--- /dev/null
+++ b/nfc/pn-local.fig
@@ -0,0 +1,30 @@
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+4 0 0 50 -1 22 12 0.0000 4 135 1080 6075 7155 Other devices\001
diff --git a/nfc/pn-shared.fig b/nfc/pn-shared.fig
new file mode 100644
index 0000000..5f983ab
--- /dev/null
+++ b/nfc/pn-shared.fig
@@ -0,0 +1,29 @@
+#FIG 3.2 Produced by xfig version 3.2.5c
+Landscape
+Center
+Metric
+A4
+100.00
+Single
+-2
+1200 2
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diff --git a/nfc/prefix.fig b/nfc/prefix.fig
new file mode 100644
index 0000000..b2ae766
--- /dev/null
+++ b/nfc/prefix.fig
@@ -0,0 +1,197 @@
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diff --git a/nfc/simseq.fig b/nfc/simseq.fig
new file mode 100644
index 0000000..f2cdc2a
--- /dev/null
+++ b/nfc/simseq.fig
@@ -0,0 +1,51 @@
+#FIG 3.2 Produced by xfig version 3.2.5c
+Landscape
+Center
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+A4
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diff --git a/nfc/sortbib.pl b/nfc/sortbib.pl
new file mode 100755
index 0000000..5e6e6be
--- /dev/null
+++ b/nfc/sortbib.pl
@@ -0,0 +1,48 @@
+#!/usr/bin/perl
+
+sub usage
+{
+ print STDERR "usage: $0 file.tex file.bib\n";
+ exit(1);
+}
+
+
+&usage unless $#ARGV == 1;
+
+($tex, $bib) = @ARGV;
+
+open(TEX, $tex) || die "$tex: $!";
+$t = join("", <TEX>);
+close TEX;
+
+open(BIB, $bib) || die "$bib: $!";
+$b = join("", <BIB>);
+close BIB;
+
+while ($t =~ /\\cite{([^}]+)}/s) {
+ for (split(/,/, $1)) {
+ next if defined $seen{$_};
+ $seen{$_} = 1;
+ push(@c, $_);
+ }
+ $t = $';
+}
+
+while ($b =~ /\\bibitem{([^}]+)}/s) {
+ $bib{$last} .= $` if defined $last;
+ $last = $1;
+ $bib{$1} = $&;
+ $b = $';
+}
+$bib{$last} .= $b if defined $last;
+
+for (@c) {
+ die "undefined citation \"$_\"" unless defined $bib{$_};
+ print $bib{$_};
+ $used{$_} = 1;
+}
+
+for (sort keys %bib) {
+ print STDERR "warning: reference \"$_\" was not used\n"
+ unless $used{$_};
+}
diff --git a/nfc/stack.fig b/nfc/stack.fig
new file mode 100644
index 0000000..6982a34
--- /dev/null
+++ b/nfc/stack.fig
@@ -0,0 +1,127 @@
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diff --git a/nfc/swp-cmp.fig b/nfc/swp-cmp.fig
new file mode 100644
index 0000000..6b7bd29
--- /dev/null
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diff --git a/nfc/swp-t.fig b/nfc/swp-t.fig
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diff --git a/nfc/swp.fig b/nfc/swp.fig
new file mode 100644
index 0000000..3d093ee
--- /dev/null
+++ b/nfc/swp.fig
@@ -0,0 +1,38 @@
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diff --git a/nfc/sys.fig b/nfc/sys.fig
new file mode 100644
index 0000000..261535c
--- /dev/null
+++ b/nfc/sys.fig
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+4 1 0 50 -1 23 12 0.0000 4 180 930 7425 4410 Data, power\001
+4 1 0 50 -1 22 12 0.0000 4 135 1245 7425 6525 ETSI TS 102 613\001
+4 1 0 50 -1 22 12 0.0000 4 135 1245 7425 4725 ETSI TS 102 211\001
+4 1 0 50 -1 22 12 0.0000 4 180 480 7425 6750 (SWP)\001
+4 1 0 50 -1 22 12 0.0000 4 135 855 5265 4725 USB/UART\001
+4 1 0 50 -1 22 12 0.0000 4 180 465 5400 5625 (TBD)\001
+4 1 0 50 -1 23 12 0.0000 4 180 930 9225 5760 Data, power\001
+4 1 0 50 -1 23 12 0.0000 4 180 930 9225 4860 Data, power\001
+4 2 0 50 -1 22 12 0.0000 4 135 690 9135 4050 Terminal\001
+4 1 0 50 -1 22 12 0.0000 4 135 345 4275 5265 CPU\001
+4 1 0 50 -1 22 12 0.0000 4 135 615 4275 5445 DM3730\001
+4 1 0 50 -1 22 12 0.0000 4 135 375 4275 5625 Host\001
+4 1 0 50 -1 22 12 0.0000 4 135 585 6300 4500 Modem\001
+4 1 0 50 -1 22 12 0.0000 4 135 600 6300 4680 PHS8/...\001
diff --git a/nfc/trf-comb.fig b/nfc/trf-comb.fig
new file mode 100644
index 0000000..9d8d2a9
--- /dev/null
+++ b/nfc/trf-comb.fig
@@ -0,0 +1,115 @@
+#FIG 3.2 Produced by xfig version 3.2.5c
+Landscape
+Center
+Metric
+A4
+100.00
+Single
+-2
+1200 2
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+ 1 1 2.00 60.00 90.00
+ 6075 1800 2700 1800 2700 3375
+2 1 1 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 3
+ 1 1 2.00 60.00 90.00
+ 6075 6075 2700 6075 2700 5400
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 6075 4275 3825 4275
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+ 1 1 2.00 60.00 90.00
+ 6075 2025 3465 2025 3465 2790
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 6075 3600 3825 3600
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+ 1 1 2.00 60.00 90.00
+ 5625 3600 5625 4500 3825 4500
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 4
+ 1 1 2.00 60.00 90.00
+ 5625 4500 5625 5850 2925 5850 2925 5400
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 6075 4725 3825 4725
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 3
+ 3600 3015 3825 3015 3825 3195
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 3735 3195 3915 3195
+2 1 0 2 0 7 50 -1 -1 0.000 0 1 -1 1 0 4
+ 1 1 2.00 60.00 90.00
+ 3555 2835 3375 2925 3150 2925 3150 3375
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 3
+ 4275 5400 4275 5175 3825 5175
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4185 5400 4365 5400
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 3
+ 4275 4905 4275 4950 3825 4950
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+ 1 1 2.00 60.00 90.00
+ 3150 5400 3150 5625 6075 5625
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
+ 2250 3375 3825 3375 3825 5400 2250 5400
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+ 1 1 2.00 60.00 90.00
+ 2925 3375 2925 2520 4950 2520
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 1 2
+ 1 1 2.00 60.00 90.00
+ 1 1 2.00 60.00 90.00
+ 5400 2700 6075 2700
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 5130 2025 5130 2385
+2 3 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+ 4950 3060 4950 2340 5400 2475 5400 2925 4950 3060
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 4
+ 1 1 2.00 60.00 90.00
+ 4950 2700 4050 2700 4050 2835 3600 2835
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 4
+ 1 1 2.00 60.00 90.00
+ 3825 4050 4275 4050 4275 2880 4950 2880
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 3825 3825 6075 3825
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
+ 7200 1575 6075 1575 6075 6300 7200 6300
+4 1 0 50 -1 22 12 0.0000 4 135 345 6525 6525 CPU\001
+4 0 0 50 -1 22 12 0.0000 4 165 840 6165 6120 GPIO_OOK\001
+4 1 0 50 -1 22 12 0.0000 4 135 315 4950 4230 nSS\001
+4 1 0 50 -1 22 12 0.0000 4 135 330 4950 4455 TXD\001
+4 1 0 50 -1 22 12 0.0000 4 165 525 4950 4680 TX_EN\001
+4 0 0 50 -1 22 12 0.0000 4 165 765 6165 5670 GPIO_IRQ\001
+4 0 0 50 -1 22 12 0.0000 4 165 750 6165 3645 SPI_MOSI\001
+4 0 0 50 -1 22 12 0.0000 4 165 750 6165 3870 SPI_MISO\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 3645 IO_7\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 3870 IO_6\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4095 IO_5\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4320 IO_4\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4545 IO_3\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4770 IO_2\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4995 IO_1\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 5220 IO_0\001
+4 2 0 50 -1 22 12 1.5708 4 165 900 3195 3465 DATA_CLK\001
+4 0 0 50 -1 22 12 1.5708 4 135 285 3195 5310 IRQ\001
+4 0 0 50 -1 22 12 1.5708 4 135 375 2970 5310 MOD\001
+4 0 0 50 -1 22 12 1.5708 4 135 360 2745 5310 OOK\001
+4 1 0 50 -1 22 12 0.0000 4 135 345 4275 4905 VDD\001
+4 1 0 50 -1 22 12 0.0000 4 135 405 4950 3555 MOSI\001
+4 1 0 50 -1 22 12 0.0000 4 135 795 4950 3780 MISO/RXD\001
+4 1 0 50 -1 22 12 0.0000 4 135 285 4950 5580 IRQ\001
+4 1 0 50 -1 22 12 0.0000 4 135 375 4950 5805 MOD\001
+4 1 0 50 -1 22 12 0.0000 4 135 360 4950 6030 OOK\001
+4 2 0 50 -1 22 12 1.5708 4 135 225 2745 3465 EN\001
+4 1 0 50 -1 22 12 1.5708 4 135 810 2520 4410 TRF7970A\001
+4 2 0 50 -1 22 12 1.5708 4 165 750 2970 3465 SYS_CLK\001
+4 1 0 50 -1 22 12 0.0000 4 135 540 4950 1755 Enable\001
+4 1 0 50 -1 22 12 0.0000 4 180 690 4950 1980 MODE[2]\001
+4 0 0 50 -1 22 12 0.0000 4 165 705 6165 1845 GPIO_EN\001
+4 0 0 50 -1 22 12 0.0000 4 180 1170 6165 2070 GPIO_MODE[2]\001
+4 0 0 50 -1 22 12 0.0000 4 165 690 6165 2745 SPI_CLK\001
+4 0 0 50 -1 22 8 0.0000 4 105 225 4995 2925 TRX\001
+4 0 0 50 -1 22 8 0.0000 4 105 150 4995 2565 RF\001
+4 0 0 50 -1 22 8 0.0000 4 105 180 4995 2745 SPI\001
+4 0 0 50 -1 22 12 0.0000 4 165 1005 6165 4770 GPIO_TX_EN\001
+4 0 0 50 -1 21 12 0.0000 4 180 1170 6165 4950 (Hold high when\001
+4 0 0 50 -1 21 12 0.0000 4 180 795 6165 5130 raising EN)\001
+4 0 0 50 -1 22 12 0.0000 4 165 660 6165 4320 SPI_nSS\001
diff --git a/nfc/trf-dm-sysclk.fig b/nfc/trf-dm-sysclk.fig
new file mode 100644
index 0000000..da1127f
--- /dev/null
+++ b/nfc/trf-dm-sysclk.fig
@@ -0,0 +1,76 @@
+#FIG 3.2 Produced by xfig version 3.2.5c
+Landscape
+Center
+Metric
+A4
+100.00
+Single
+-2
+1200 2
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
+ 7200 2475 6075 2475 6075 6300 7200 6300
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+ 1 1 2.00 60.00 90.00
+ 6075 5850 2925 5850 2925 5400
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 3825 3825 6075 3825
+2 1 1 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 3
+ 1 1 2.00 60.00 90.00
+ 6075 6075 2700 6075 2700 5400
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
+ 2250 3375 3825 3375 3825 5400 2250 5400
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4050 4950 3825 4950
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4050 5175 3825 5175
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 3825 3600 4050 3600
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4050 4725 3825 4725
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4050 4500 3825 4500
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 3150 3060 3150 3375
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 4500 4275 3825 4275
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 2700 3060 2700 3375
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 3825 4050 4050 4050
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 5
+ 1 1 2.00 60.00 90.00
+ 2925 3375 2925 2700 5625 2700 5625 4050 6075 4050
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 3150 5400 3150 5625
+4 1 0 50 -1 22 12 0.0000 4 135 345 6525 6525 CPU\001
+4 0 0 50 -1 22 12 0.0000 4 165 915 6165 4095 SHIFT_CLK\001
+4 0 0 50 -1 22 12 0.0000 4 165 735 6165 3870 SHIFT_IN\001
+4 0 0 50 -1 22 12 0.0000 4 165 810 6165 5895 MOD_OUT\001
+4 0 0 50 -1 22 12 0.0000 4 165 840 6165 6120 GPIO_OOK\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 3645 IO_7\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 3870 IO_6\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4095 IO_5\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4320 IO_4\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4545 IO_3\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4770 IO_2\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4995 IO_1\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 5220 IO_0\001
+4 2 0 50 -1 22 12 1.5708 4 165 900 3195 3465 DATA_CLK\001
+4 0 0 50 -1 22 12 1.5708 4 135 285 3195 5310 IRQ\001
+4 0 0 50 -1 22 12 1.5708 4 135 375 2970 5310 MOD\001
+4 0 0 50 -1 22 12 1.5708 4 135 360 2745 5310 OOK\001
+4 1 0 50 -1 22 12 0.0000 4 135 315 4275 4230 nSS\001
+4 1 0 50 -1 22 12 0.0000 4 165 690 4950 3780 RX_MOD\001
+4 1 0 50 -1 22 12 0.0000 4 165 675 4950 5805 TX_MOD\001
+4 1 0 50 -1 22 12 0.0000 4 135 360 4950 6030 OOK\001
+4 2 0 50 -1 22 12 1.5708 4 135 225 2745 3465 EN\001
+4 2 0 50 -1 22 12 1.5708 4 165 750 2970 3465 SYS_CLK\001
+4 1 0 50 -1 22 12 1.5708 4 135 810 2520 4410 TRF7970A\001
+4 1 0 50 -1 22 12 0.0000 4 135 105 3150 3015 L\001
+4 0 0 50 -1 22 12 0.0000 4 135 105 4545 4320 L\001
+4 1 0 50 -1 22 12 0.0000 4 135 120 2700 3015 H\001
+4 1 0 50 -1 22 12 0.0000 4 165 780 4950 2655 NFC_CLK\001
diff --git a/nfc/trf-dm1-rx.fig b/nfc/trf-dm1-rx.fig
new file mode 100644
index 0000000..bd28ce0
--- /dev/null
+++ b/nfc/trf-dm1-rx.fig
@@ -0,0 +1,71 @@
+#FIG 3.2 Produced by xfig version 3.2.5c
+Landscape
+Center
+Metric
+A4
+100.00
+Single
+-2
+1200 2
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
+ 7200 2475 6075 2475 6075 6300 7200 6300
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 3825 3825 6075 3825
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 3825 4050 6075 4050
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
+ 2250 3375 3825 3375 3825 5400 2250 5400
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4050 4950 3825 4950
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4050 5175 3825 5175
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 3825 3600 4050 3600
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4050 4725 3825 4725
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4050 4500 3825 4500
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 3150 3060 3150 3375
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 3
+ 3150 5400 3150 5625 3375 5625
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 2925 3375 2925 3150
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 4500 4275 3825 4275
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 2700 3060 2700 3375
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 2925 5625 2925 5400
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 2700 5625 2700 5400
+4 1 0 50 -1 22 12 0.0000 4 135 345 6525 6525 CPU\001
+4 0 0 50 -1 22 12 0.0000 4 165 915 6165 4095 SHIFT_CLK\001
+4 0 0 50 -1 22 12 0.0000 4 165 735 6165 3870 SHIFT_IN\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 3645 IO_7\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 3870 IO_6\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4095 IO_5\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4320 IO_4\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4545 IO_3\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4770 IO_2\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4995 IO_1\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 5220 IO_0\001
+4 2 0 50 -1 22 12 1.5708 4 165 900 3195 3465 DATA_CLK\001
+4 0 0 50 -1 22 12 1.5708 4 135 285 3195 5310 IRQ\001
+4 0 0 50 -1 22 12 1.5708 4 135 375 2970 5310 MOD\001
+4 0 0 50 -1 22 12 1.5708 4 135 360 2745 5310 OOK\001
+4 1 0 50 -1 22 12 0.0000 4 135 315 4275 4230 nSS\001
+4 0 0 50 -1 22 12 0.0000 4 135 105 3420 5670 ?\001
+4 1 0 50 -1 22 12 0.0000 4 165 780 4950 3780 RX_DATA\001
+4 1 0 50 -1 22 12 0.0000 4 165 660 4950 4005 RX_CLK\001
+4 2 0 50 -1 22 12 1.5708 4 135 225 2745 3465 EN\001
+4 2 0 50 -1 22 12 1.5708 4 165 750 2970 3465 SYS_CLK\001
+4 1 0 50 -1 22 12 1.5708 4 135 810 2520 4410 TRF7970A\001
+4 1 0 50 -1 22 12 0.0000 4 135 105 3150 3015 L\001
+4 0 0 50 -1 22 12 0.0000 4 135 105 4545 4320 L\001
+4 1 0 50 -1 22 12 0.0000 4 135 120 2700 3015 H\001
diff --git a/nfc/trf-kl26.fig b/nfc/trf-kl26.fig
new file mode 100644
index 0000000..ebf03d5
--- /dev/null
+++ b/nfc/trf-kl26.fig
@@ -0,0 +1,111 @@
+#FIG 3.2 Produced by xfig version 3.2.5c
+Landscape
+Center
+Metric
+A4
+100.00
+Single
+-2
+1200 2
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
+ 7200 1575 6075 1575 6075 6300 7200 6300
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+ 1 1 2.00 60.00 90.00
+ 6075 1800 2700 1800 2700 3375
+2 1 1 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 3
+ 1 1 2.00 60.00 90.00
+ 6075 6075 2700 6075 2700 5400
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 6075 4275 3825 4275
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 6075 3600 3825 3600
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 4
+ 1 1 2.00 60.00 90.00
+ 5625 4500 5625 5850 2925 5850 2925 5400
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 6075 4725 3825 4725
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 3
+ 4275 5400 4275 5175 3825 5175
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4185 5400 4365 5400
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+ 1 1 2.00 60.00 90.00
+ 3150 5400 3150 5625 6075 5625
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
+ 2250 3375 3825 3375 3825 5400 2250 5400
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 3825 3825 6075 3825
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 6075 4500 3825 4500
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 3825 4050 6075 4050
+2 1 0 2 0 7 50 -1 -1 0.000 0 1 -1 1 0 3
+ 1 1 2.00 60.00 90.00
+ 6075 2925 3150 2925 3150 3375
+2 1 0 2 0 7 50 -1 -1 0.000 0 1 -1 1 0 3
+ 1 1 2.00 60.00 90.00
+ 2925 3375 2925 2025 6075 2025
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+ 1 1 2.00 60.00 90.00
+ 5625 3825 5625 3375 6075 3375
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 4
+ 1 1 2.00 60.00 90.00
+ 6075 2475 5625 2475 5625 2250 6075 2250
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 6075 4950 3825 4950
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 7200 4590 7200 5040
+4 1 0 50 -1 22 12 0.0000 4 135 405 6525 6525 KL26\001
+4 0 0 50 -1 22 12 0.0000 4 165 840 6165 6120 GPIO_OOK\001
+4 1 0 50 -1 22 12 0.0000 4 135 315 4950 4230 nSS\001
+4 1 0 50 -1 22 12 0.0000 4 135 330 4950 4455 TXD\001
+4 1 0 50 -1 22 12 0.0000 4 165 525 4950 4680 TX_EN\001
+4 0 0 50 -1 22 12 0.0000 4 165 765 6165 5670 GPIO_IRQ\001
+4 0 0 50 -1 22 12 0.0000 4 165 840 6165 3645 SPI0_MOSI\001
+4 0 0 50 -1 22 12 0.0000 4 165 840 6165 3870 SPI0_MISO\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 3645 IO_7\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 3870 IO_6\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4095 IO_5\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4320 IO_4\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4545 IO_3\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4770 IO_2\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4995 IO_1\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 5220 IO_0\001
+4 2 0 50 -1 22 12 1.5708 4 165 900 3195 3465 DATA_CLK\001
+4 0 0 50 -1 22 12 1.5708 4 135 285 3195 5310 IRQ\001
+4 0 0 50 -1 22 12 1.5708 4 135 375 2970 5310 MOD\001
+4 0 0 50 -1 22 12 1.5708 4 135 360 2745 5310 OOK\001
+4 1 0 50 -1 22 12 0.0000 4 135 405 4950 3555 MOSI\001
+4 1 0 50 -1 22 12 0.0000 4 135 285 4950 5580 IRQ\001
+4 1 0 50 -1 22 12 0.0000 4 135 375 4950 5805 MOD\001
+4 1 0 50 -1 22 12 0.0000 4 135 360 4950 6030 OOK\001
+4 2 0 50 -1 22 12 1.5708 4 135 225 2745 3465 EN\001
+4 1 0 50 -1 22 12 1.5708 4 135 810 2520 4410 TRF7970A\001
+4 2 0 50 -1 22 12 1.5708 4 165 750 2970 3465 SYS_CLK\001
+4 0 0 50 -1 22 12 0.0000 4 165 780 6165 4095 SPI1_SCK\001
+4 0 0 50 -1 22 12 0.0000 4 165 855 6165 4320 SPI0_PCS0\001
+4 0 0 50 -1 22 12 0.0000 4 165 780 6165 2970 SPI0_SCK\001
+4 0 0 50 -1 22 12 0.0000 4 165 840 6165 3420 SPI1_MISO\001
+4 0 0 50 -1 22 12 0.0000 4 165 840 6165 4545 SPI1_MOSI\001
+4 0 0 50 -1 22 12 0.0000 4 165 1005 6165 4770 GPIO_TX_EN\001
+4 1 0 50 -1 22 12 0.0000 4 135 450 4950 2880 SCLK\001
+4 1 0 50 -1 22 12 0.0000 4 135 795 4950 3780 MISO/RXD\001
+4 1 0 50 -1 22 12 0.0000 4 165 765 4950 4005 TRX_CLK\001
+4 1 0 50 -1 22 12 0.0000 4 135 540 4950 1755 Enable\001
+4 0 0 50 -1 22 12 0.0000 4 165 705 6165 1845 GPIO_EN\001
+4 0 0 50 -1 22 12 0.0000 4 135 630 6165 2070 EXTAL0\001
+4 1 0 50 -1 22 12 0.0000 4 165 780 4950 1980 NFC_CLK\001
+4 2 0 50 -1 22 12 0.0000 4 135 420 5535 2430 SELF\001
+4 0 0 50 -1 22 12 0.0000 4 165 855 6165 2295 SPI1_PCS0\001
+4 0 0 50 -1 22 12 0.0000 4 165 900 6165 2520 GPIO_SELF\001
+4 0 0 50 -1 22 12 0.0000 4 165 825 6165 4995 GPIO_IO_1\001
+4 0 0 50 -1 21 12 0.0000 4 180 795 7290 4950 raising EN)\001
+4 0 0 50 -1 21 12 0.0000 4 180 1170 7290 4770 (Hold high when\001
+4 1 0 50 -1 22 12 0.0000 4 165 345 4950 4905 IO_1\001
diff --git a/nfc/trf-sdm.fig b/nfc/trf-sdm.fig
new file mode 100644
index 0000000..ef575e7
--- /dev/null
+++ b/nfc/trf-sdm.fig
@@ -0,0 +1,74 @@
+#FIG 3.2 Produced by xfig version 3.2.5c
+Landscape
+Center
+Metric
+A4
+100.00
+Single
+-2
+1200 2
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
+ 7200 2475 6075 2475 6075 6300 7200 6300
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 6075 4725 3825 4725
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 3825 4050 6075 4050
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
+ 2250 3375 3825 3375 3825 5400 2250 5400
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4050 4950 3825 4950
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4050 5175 3825 5175
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 3825 3600 4050 3600
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 3825 3825 4050 3825
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 3150 5400 3150 5625
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 2925 5400 2925 5625
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 2700 5400 2700 5625
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 3150 3060 3150 3375
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 4500 4275 3825 4275
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 2925 3150 2925 3375
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 6075 4500 3825 4500
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 2700 3060 2700 3375
+4 0 0 50 -1 22 12 0.0000 4 165 660 6165 4320 SPI_nSS\001
+4 0 0 50 -1 22 12 0.0000 4 165 915 6165 4095 SHIFT_CLK\001
+4 0 0 50 -1 22 12 0.0000 4 165 1005 6165 4770 GPIO_TX_EN\001
+4 0 0 50 -1 22 12 0.0000 4 165 915 6165 4545 SHIFT_OUT\001
+4 1 0 50 -1 22 12 0.0000 4 135 345 6525 6525 CPU\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 3645 IO_7\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 3870 IO_6\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4095 IO_5\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4320 IO_4\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4545 IO_3\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4770 IO_2\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4995 IO_1\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 5220 IO_0\001
+4 2 0 50 -1 22 12 1.5708 4 165 900 3195 3465 DATA_CLK\001
+4 0 0 50 -1 22 12 1.5708 4 135 285 3195 5310 IRQ\001
+4 0 0 50 -1 22 12 1.5708 4 135 375 2970 5310 MOD\001
+4 0 0 50 -1 22 12 1.5708 4 135 360 2745 5310 OOK\001
+4 2 0 50 -1 22 12 1.5708 4 135 225 2745 3465 EN\001
+4 2 0 50 -1 22 12 1.5708 4 165 750 2970 3465 SYS_CLK\001
+4 1 0 50 -1 22 12 1.5708 4 135 810 2520 4410 TRF7970A\001
+4 1 0 50 -1 22 12 0.0000 4 165 765 5175 4455 TX_DATA\001
+4 1 0 50 -1 22 12 0.0000 4 165 525 5175 4680 TX_EN\001
+4 1 0 50 -1 22 12 0.0000 4 165 645 5175 4005 TX_CLK\001
+4 0 0 50 -1 22 12 0.0000 4 135 105 4545 4320 L\001
+4 1 0 50 -1 22 12 0.0000 4 135 315 4275 4230 nSS\001
+4 1 0 50 -1 22 12 0.0000 4 135 105 3150 3015 L\001
+4 1 0 50 -1 22 12 0.0000 4 135 120 2700 3015 H\001
diff --git a/nfc/trf-stack.fig b/nfc/trf-stack.fig
new file mode 100644
index 0000000..51f4908
--- /dev/null
+++ b/nfc/trf-stack.fig
@@ -0,0 +1,84 @@
+#FIG 3.2 Produced by xfig version 3.2.5c
+Landscape
+Center
+Metric
+A4
+100.00
+Single
+-2
+1200 2
+2 2 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+ 2925 8100 4275 8100 4275 7650 2925 7650 2925 8100
+2 2 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+ 2925 7200 4275 7200 4275 6750 2925 6750 2925 7200
+2 2 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+ 2925 6300 4275 6300 4275 5850 2925 5850 2925 6300
+2 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 60.00
+ 3375 7200 3375 7650
+2 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 60.00
+ 3825 7650 3825 7200
+2 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 60.00
+ 3375 6300 3375 6750
+2 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 60.00
+ 3825 6750 3825 6300
+2 2 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+ 2925 5400 4275 5400 4275 4950 2925 4950 2925 5400
+2 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 60.00
+ 3375 5400 3375 5850
+2 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 60.00
+ 3825 5850 3825 5400
+2 2 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+ 2925 4500 4275 4500 4275 4050 2925 4050 2925 4500
+2 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 60.00
+ 3375 4500 3375 4950
+2 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 60.00
+ 3825 4950 3825 4500
+2 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 60.00
+ 4275 4275 4725 4275
+2 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 60.00
+ 2475 4275 2925 4275
+2 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 60.00
+ 3825 6570 4725 6570
+2 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 60.00
+ 3825 7470 4725 7470
+2 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 60.00
+ 2475 6480 3375 6480
+2 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 60.00
+ 2475 7380 3375 7380
+2 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 60.00
+ 3375 8100 3375 8550
+2 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 60.00
+ 3825 8550 3825 8100
+2 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 5
+ 1 1 2.00 60.00 60.00
+ 3825 5670 4500 5670 4500 4770 4050 4770 4050 4500
+4 1 0 50 -1 22 12 0.0000 4 135 900 3600 7920 Modulation\001
+4 1 0 50 -1 22 12 0.0000 4 135 1050 3600 6120 Packetization\001
+4 1 0 50 -1 22 12 0.0000 4 180 900 3600 5220 Parity, CRC\001
+4 1 0 50 -1 22 12 0.0000 4 135 375 3600 4320 FIFO\001
+4 0 0 50 -1 22 12 0.0000 4 135 1365 4860 4320 Standard: frames\001
+4 2 0 50 -1 22 12 0.0000 4 135 1365 2385 4320 Standard: frames\001
+4 0 0 50 -1 22 12 0.0000 4 180 1905 4815 7515 DM0: Digitized envelope\001
+4 0 0 50 -1 22 12 0.0000 4 135 1965 4815 6615 DM1: Data bits and clock\001
+4 2 0 50 -1 22 12 0.0000 4 165 1785 2385 7425 DM0, DM1: Modulation\001
+4 2 0 50 -1 22 12 0.0000 4 135 1980 2385 6525 SDM: Data bits and clock\001
+4 0 0 50 -1 22 12 0.0000 4 180 2010 4590 5220 SDM: Unchecked packets\001
+4 1 0 50 -1 22 12 0.0000 4 135 210 3375 8730 TX\001
+4 1 0 50 -1 22 12 0.0000 4 135 225 3825 8730 RX\001
+4 1 0 50 -1 22 12 0.0000 4 180 585 3600 7020 Coding\001
diff --git a/nfc/trf-std.fig b/nfc/trf-std.fig
new file mode 100644
index 0000000..9f3f0b4
--- /dev/null
+++ b/nfc/trf-std.fig
@@ -0,0 +1,82 @@
+#FIG 3.2 Produced by xfig version 3.2.5c
+Landscape
+Center
+Metric
+A4
+100.00
+Single
+-2
+1200 2
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
+ 7200 2475 6075 2475 6075 6300 7200 6300
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 6075 3600 3825 3600
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 3825 3825 6075 3825
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+ 1 1 2.00 60.00 90.00
+ 6075 2925 3150 2925 3150 3375
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+ 1 1 2.00 60.00 90.00
+ 6075 2700 2700 2700 2700 3375
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 2
+ 1 1 2.00 60.00 90.00
+ 6075 4275 3825 4275
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 1 0 3
+ 1 1 2.00 60.00 90.00
+ 3150 5400 3150 5625 6075 5625
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 3
+ 3825 4725 4500 4725 4500 4545
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 3
+ 3825 4950 4500 4950 4500 4725
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 3
+ 3825 5175 4500 5175 4500 5400
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 4410 5400 4590 5400
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
+ 4680 4635 4770 4635 4770 5265 4680 5265
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
+ 2250 3375 3825 3375 3825 5400 2250 5400
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 3825 4050 4050 4050
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 3825 4500 4050 4500
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 2925 5400 2925 5625
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 2700 5400 2700 5625
+2 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 2925 3150 2925 3375
+4 0 0 50 -1 22 12 0.0000 4 165 750 6165 3870 SPI_MISO\001
+4 0 0 50 -1 22 12 0.0000 4 165 750 6165 3645 SPI_MOSI\001
+4 0 0 50 -1 22 12 0.0000 4 165 795 6165 2970 SPI_SCLK\001
+4 0 0 50 -1 22 12 0.0000 4 165 705 6165 2745 GPIO_EN\001
+4 0 0 50 -1 22 12 0.0000 4 165 750 6165 5670 GPIO_INT\001
+4 0 0 50 -1 22 12 0.0000 4 165 660 6165 4320 SPI_nSS\001
+4 1 0 50 -1 22 12 0.0000 4 135 345 6525 6525 CPU\001
+4 1 0 50 -1 23 12 1.5708 4 180 750 4995 4950 Power-up\001
+4 1 0 50 -1 23 12 1.5708 4 180 1080 5175 4950 configuration\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 3645 IO_7\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 3870 IO_6\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4095 IO_5\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4320 IO_4\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4545 IO_3\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4770 IO_2\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 4995 IO_1\001
+4 2 0 50 -1 22 12 0.0000 4 165 345 3735 5220 IO_0\001
+4 2 0 50 -1 22 12 1.5708 4 165 900 3195 3465 DATA_CLK\001
+4 0 0 50 -1 22 12 1.5708 4 135 285 3195 5310 IRQ\001
+4 0 0 50 -1 22 12 1.5708 4 135 375 2970 5310 MOD\001
+4 0 0 50 -1 22 12 1.5708 4 135 360 2745 5310 OOK\001
+4 1 0 50 -1 22 12 0.0000 4 135 345 4500 4500 VDD\001
+4 1 0 50 -1 22 12 0.0000 4 135 540 4950 2655 Enable\001
+4 1 0 50 -1 22 12 0.0000 4 135 450 4995 2880 SCLK\001
+4 1 0 50 -1 22 12 0.0000 4 135 405 4950 3555 MOSI\001
+4 1 0 50 -1 22 12 0.0000 4 135 405 4950 3780 MISO\001
+4 1 0 50 -1 22 12 0.0000 4 135 315 4950 4230 nSS\001
+4 1 0 50 -1 22 12 0.0000 4 135 285 5625 5580 IRQ\001
+4 2 0 50 -1 22 12 1.5708 4 135 225 2745 3465 EN\001
+4 2 0 50 -1 22 12 1.5708 4 165 750 2970 3465 SYS_CLK\001
+4 1 0 50 -1 22 12 1.5708 4 135 810 2520 4410 TRF7970A\001