A Digital Comparator (DCMP) compares two binary values, the positive terminal input IN+ and the negative terminal input IN-. When the comparison is complete, it will output a 1 on EQ if the inputs are equal or 1 on OUT+ if IN+ is greater than IN-. The second function is Pulse Width Modulator (PWM). In this mode, the positive terminal is compared with the negative terminal input and the result outputs on OUT+ and OUT-. Both OUT+ and OUT- are the same logic with a deadband in between. This is to drive external PMOS and NMOS gates such that an external circuit is source directly from the supply.

Activation

Erase wire SHARED PD from VDD.
Set Properties -> DCMP/PWM power register to ‘Power on’.

Input

IN+ and IN- are the positive and negative terminal inputs. They are connected automatically when a block is activated.
MTRX SEL #0, 1 are the selection nodes for DCMP/PWM internal registers. These nodes use binary code for choosing the registers
CLK: At the rising edge, All 8 bits of IN+ and IN- are compared simultaneously and outputs updated.

Table 1. Matrix Select Bits to Register

MTRX SEL#1 MTRX SEL#0 Chosen Register # DCMP0 Chosen Register # DCMP1

LOW LOW 0 3

LOW HIGH 1 2

HIGH LOW 2 1

HIGH HIGH 3 0

MTRX SEL#1	MTRX SEL#0	Chosen Register # DCMP0	Chosen Register # DCMP1
LOW	LOW	0	3
LOW	HIGH	1	2
HIGH	LOW	2	1
HIGH	HIGH	3	0

Parameters

DCMP/PWM power down:

Activate or De-activate the DCMP/PWM and prevent idle current consumption.

Function selection:

Select between PWM and DCMP modes.

• In DCMP mode: Outputs are EQ and OUT+;

• In PWM mode: Outputs are OUT+ and OUT-;

PD sync to clock:

Dynamically power down the DCMP when the input CLK is halted.

Clock source:

Use the same CLK as the ADC or an external EXT. CLK0 source
For more information, see OSC Detailed Info

Clock invert:

Invert input CLK so the DCMP/PWM is falling edge triggered.

Duty cycle:

The duty cycle (DC) cannot range from 0 to 100%, instead there is a shift below or above. Choose the setting that best fits the application.

• 0-99.6%: DC ranges from 0% to 99.6% and is determined as IN/256;

• 0.39-100%: DC ranges from 0.39% to 100% and is determined as (IN+1)/256.;

PWM deadband:

Deadband is the time lag between OUT+ and OUT-‘s rising and falling edges. Options are 10ns, 20ns, 40ns and 80ns.

Register 0-3:

These Registers can be used as IN- or IN+ sources. There are four registers, each 8-bits and are common through all three DCMP/PWMs . To use them as sources, configure IN+ or IN- selector to ‘Register X’ or ‘Register selected through the matrix’. For ‘Register selected through matrix’, inputs MTRX_SEL #0 and #1 are the select bits. See Table 1 above

IN+ selector:

Positive Terminal Input of the DCMP/PWM. Each DCMP has different options. See Table 2 below

IN- selector:

Negative Terminal Input of the DCMP/PWM. Each DCMP has different options. See Table 2 below

Table 2. DCMP IN+ and IN- selector

Selector DCMP/PWM0 DCMP/PWM1 DCMP/PWM2

IN+ ADC [7:0] ADC [7:0] ADC [7:0]

SPI [15:8] SPI [7:0] SPI [15:8]

FSM0 [7:0] FSM1 [7:0] FSM1 [7:0]

Register selected through the matrix Register 1 Register 3

IN- SPI [7:0] SPI [15:8] SPI [7:0]

CNT8 [7:0] CNT9 [7:0] FSM0 [7:0]

FSM1 [7:0] FSM0 [7:0] CNT8 [7:0]

Register 0 Register selected through the matrix Register 2

Selector	DCMP/PWM0	DCMP/PWM1	DCMP/PWM2
IN+	ADC [7:0]	ADC [7:0]	ADC [7:0]
	SPI [15:8]	SPI [7:0]	SPI [15:8]
	FSM0 [7:0]	FSM1 [7:0]	FSM1 [7:0]
	Register selected through the matrix	Register 1	Register 3
IN-	SPI [7:0]	SPI [15:8]	SPI [7:0]
	CNT8 [7:0]	CNT9 [7:0]	FSM0 [7:0]
	FSM1 [7:0]	FSM0 [7:0]	CNT8 [7:0]
	Register 0	Register selected through the matrix	Register 2