The Non-Volatile Memory (NVM) holds all configuration bits of the PAK device. The NVM is broken into four banks where the first three can be Locked, preventing subsequent reads or writes of the chip’s NVM sequence.
The I2C read protection is prevented during emulation, but will be configured if programmed.
The memory space is divided into four banks, each of which has 512bits (64bytes). There is the option that allows the user to define rules for reading and writing bits in each of these banks via I2C.
Read protection: if the system provides any read commands to the addresses in locked banks, the device will respond with ‘FFH’ in data field.
Write protection: if the system provides any write commands to the addresses in locked banks, the device will acknowledge these commands, but will not do internal writes to the register space.
• Unlocked: no read or write protection;
• Locked for read bits <1535:0>: Bank 0/1/2 is locked for read;
• Locked for write bits <1535:0>: Bank 0/1/2 is locked for write;
• Locked for read and write bits <1535:0>: Bank 0/1/2 is locked for read and write;
An 16-bit NVM location used to differentiate the NVM code programmed onto the chip. The Pattern ID is the only information accessible from a NVM locked chip.
General Power, Analog and Quick Charge Options can be configured here.
The bandgap sources the voltage reference VREF. The bandgap is auto powered on and off when analog components are enabled or disabled. The ‘bandgap output delay time’ can be bypassed if the bandgap is forced on, improving response time of analog comparators.
There is an additional delay gating the analog comparator output after the bandgap has become valid. This gives time for the charge pump and regulator to settle before obtaining valid comparator data. The VREF and Ring OSC components are NOT gated by this output delay. If Forced bandgap on is Enabled, this delay is bypassed.
• Auto-Delay: The additional delay will be either 100 or 550 us depending on the ‘Power Supply Control’ and VDD.
- If Power Supply Control is ‘Charge Pump always OFF’, then the delay will be 100us.
- If Power Supply Control is ‘Charge Pump always ON’, then the delay will be 550us.
- If Power Supply Control is ‘Charge Pump automatically ON/OFF’, then the delay will be 550us if VDD < 2.7 and 100us if VDD > 2.7.
- If Power Supply Control is ‘VDD directly to analog blocks’, then the delay will be 550us.
• 100us:
• 550us: select if charge pump is needed.
Analog components are powered by a bandgap which operates at 1.8V. This voltage is maintained by a regulator and charge pump which are enabled and disabled in accordance with bandgap usage and VDD levels. The charge pump is not necessary for VDDs greater than 2.7V. The regulator and charge pump can be forced on by Enabling ‘Force Bandgap On’ or bypassed by selecting ‘VDD directly to analog block’. Select the correct setting based on the device operating range.
• VDD directly to analog block: For VDD < 1.9V. The Regulator and Charge Pump are both off and bypassed.
• Regulator and Charge Pump automatic ON/OFF: For 1.9V < VDD < 5.5V. If VDD is less than 2.7V, the Charge Pump will turn ON. If VDD is greater than 2.7V the Charge Pump will turn OFF.
• Regulator auto ON/OFF and Charge Pump always ON: For 3.0 < VDD < 5.5V.
• Regulator auto ON/OFF and Charge Pump always OFF: For 1.7 < VDD < 3.0.
During the POR sequence, a 2.6kΩ resistor is connected in parallel to any configured pull-up/down resistors. The 10K, 100K and 1M GPIO Pull-Up/Pull-Down resistors are not enabled until POR so the quick-charge option can help settle the initial voltage faster, especially if there is significant capacitance.