The SLG46532 GreenPAK5 is Silego’s fifth generation GreenPAK Product. It is a one-time programmable Mixed signal array available in a small 2mm x 3mm TDFN-20 package.
• Logic & mixed signal circuits;
• Highly versatile macro cells;
• Read back protection (Read lock);
• 1.8 V (±5%) to 5 V (±10%) supply;
• Operating temperature range: -40°C to 85°C;
• RoHS compliant / Halogen-free;
• 20-pin STQFN: 2 × 3 × 0.55 mm, 0.4 mm pitch;
The SLG46532 provides a small, low power component for commonly used mixed-signal functions. The user creates their circuit
design by programming the one time Non-Volatile Memory (NVM) to configure the interconnect logic, the I/O Pins and the macro
cells of the SLG46532. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a very
small, low power single integrated circuit.
The additional power supply (VDD2) on the SLG46532 provides the ability to interface two independent voltage domains within
the same design. Users can configure pins, dedicated to each power supply, as inputs, outputs, or both (controlled dynamically
by internal logic) to both VDD and VDD2 voltage domains. Using the available macro-cells designers can implement mixed-signal
functions bridging both domains or simply pass through level-translation in both High to Low and Low to High directions.
The macro cells in the device include the following:
• Four Analog Comparators (ACMP)
• Two Voltage References (Vref)
• Seventeen Combination Function Macrocells
- Three Selectable DFF/Latch or 2-bit LUTs
- One Selectable Continuous DFF/Latch or 3-bit LUT
- Four Selectable DFF/Latch or 3-bit LUTs
- One Selectable Pipe Delay or 3-bit LUT
- One Selectable Programmable Function Generator or 2-bit LUT
- Five 8-bit delays/counters or 3-bit LUTs
- Two 16-bit delays/counters or 4-bit LUTs
• State Machine
- Eight States
- Flexible input logic from state transitions
• Serial Communications
- I2C Protocol compliant
• Pipe Delay – 16 stage/3 output (Part of Combination Function Macrocell)
• Programmable Delay
• Additional Logic Functions
- Two Deglitch Filters with Edge Detectors
- One Inverter
• Two Oscillators (OSC)
- Configurable 25 kHz/2 MHz
- 25MHz Ring Oscillator
• Eight Byte RAM + OTP User Memory
- RAM Memory space that is readable and writeable via I2C
- User defined initial values transferred from OTP