The Pipe Delay is a 16 stage delay composed of 16 DFFs. Three inputs from the matrix, Input (IN), Clock (CLK) and Reset (nRST) control Pipe Delay behavior. The three outputs (1 PIPE OUT, OUT0 and OUT1) provide user selectable options for 1 – 16 stages of delay.

For correct Pipe Delay functionality nReset (nRST) input should be HIGH. If nReset (nRST) input is LOW the Pipe Delay is in a reset state and all outputs are LOW.

Description

The pipe delay cell is built from 16 D Flip-Flop logic cells that are tied in series where the output (Q) of each DFF goes to the input of the next DFF. The three macrocell outputs (1 PIPE OUT, OUT0 and OUT1) select which stage of the pipe delay to output. 1 PIPE OUT is always connected to the first DFF, while OUT0/1 are user selectable.

The pipe delay can be configured as a clock divider by setting OUT1’s output polarity to be negative and feeding nOUT1 into IN. The divider will be 2x the register value chosen in OUT1 PD num for a max divider of 32.

Parameters

OUT0 PD num:

1-16 Choose the number of CK rising edges before the IN propagates to OUT0;

OUT1 PD num:

1-16 Choose the number of CK rising edges before the IN propagates to OUT1;

OUT1 output polarity:

A clock divider can be made by setting OUT1 to inverted, wiring OUT1 to IN, and choosing OUT1 PD num to be half of your desired divider, ie. if you want a /4, choose OUT1 PD num to be 2.

• Non-inverted(OUT1);

• Inverted (nOUT1);