A Counter/Delay (CNT/DLY) macrocell is a multi-function component. Modes are counter, delay or finite state machine (FSM). Each CNT/DLY component has a different combination of the above modes. As a counter, the macrocell will count to the given register value and create a pulse when it has reached the value. A delay will delay a rising and/or falling edge for the duration of the register value. As a finite state machine, the counter data can be manipulated up or down.
Choose counter for a positive pulse every X seconds (e.g. a Frequency divider). Choose delay for postponing the rising/falling edge of a signal (e.g. a Deglitching circuit).
The length of Counter/Delay period. CNT/DLY bit widths are 14-bit or 8-bit, from 1 to 16383 or 1 to 255 respectively. It is recommended to use larger counter data values for less error.
Calculate Delay time with this formula where Counter Data is the previous parameter, CLK Input Frequency is the frequency of the selected Clock Source and Offset is the asynchronous time offset between the input signal and the first clock pulse.
• Counter time: [(Counter data + 1) / CLK input frequency – Offset];
• Delay time: [(Counter data + 1) / CLK input frequency – Offset];
Same parameter as power control in the RC OSC macro-cell. For counters, it is recommended to use Forced power-on. It it not necessary in delay mode since the OSC will automatically start up if any delay block sees an input.
The COUNTER logic cells can reset if needed. Configure the Reset Source as an Edge Detect to enable this function. The COUNTER will be reset when the configured edge (configured in the Edge Select section) appears on the RESET IN node. The initial output after reset is High for the duration of one clock cycle.
In delay mode only, select which edge to delay: falling, rising, or both. If the input noise < delay time, the noise would be filtered out. This is an example of deglitching.
• Both edges: have delay time X;
• Falling edge: only delayed by time X;
• Rising edge: only delayed by time X;
Another mode is the finite state machine (FSM). In FSM mode, the user may control the counter value using macro-cell inputs “UP, KEEP, LOAD” . The FSM count value is also input to a digital comparator (DCMP) or an output of the analog-to-digital converter (ADC) or Serial-to=Parallel Converter (S2P).
UP: macro-cell input ‘UP’ is a count direction controller. A digital high sets the FSM to count up in value. A digital low sets the FSM to count down in value and both will wrap around at 0 or maximum.
KEEP: macro-cell input ‘KEEP’ is a latching mechanism. A digital high latches the current value in FSM until ‘KEEP’ is released low. A digital low resumes normal operation where a clock input will increment or decrement its counter value.
LOAD: the Load signal will force the Counter to load the data written in its register configuration when it is in a HIGH state.
• Counter data source: The FSM data will start at this number. When reaching 0 or max14-bit/8-bit the FSM will not reload this value but instead wraps around.;
• ADC PAROUT source: Loaded every time the FSM reaches 0 or max14bit/8bit;
• S2P: S2P PAR output bits 7 down-to 0 which is loaded every time the FSM reaches 0 or max14bit/8bit;
For more detailed information, see datasheet section 13.4 Counter Timing
ALL Counter/Delays have the typical CLK/4/8/12 and a variety of EXT CLK and another CNT/DLY source (view table below). Take advantage of the variety to mix and match delay times.
Table 1.
| Macrocell | Bit-Width | CNT/DLY | EXT CLK |
|---|---|---|---|
| CNT/DLY0 | 14 | 14-bit CNT/DLY1 | Yes |
| CNT/DLY1 | 14 | 14-bit CNT/DLY2 | Yes |
| CNT/DLY2 | 14 | 8-bit CNT/DLY3 | Yes |
| CNT/DLY3 | 8 | 14-bit CNT/DLY0 | Yes |
COUNTER/DELAYs 0 and 1 have an external clock input combined with DLY IN. The option of the delay with an external clock is not available for these logic cells.
Both Counter and Delay configurations can be sourced by an internal or external oscillator. Clock (RC OSC) without divider connections are not shown. (See OSC Info block for more information on the different CLK sources.)
CNT3/DLY3 EDGE DETECT output will generate short (10-20 ns) pulse after the defined edge (Edge select configuration) was detected on its DLY IN input.