The 3 digital comparators / pulse width modulators of the GreenPAK2 chip use 8-bit data for their operation. This datacan be taken from the ADC, S2P, FSM0, and COUNTER1 or from logic cells’ internal registers.

Every DCMP/PWM has the following configurable options:

• Power;

• Clock invert;

• Output range;

• PWM deadband;

• Register 0-3;

• IN+ selector;

• IN- selector;

• ADC/PWM/RCO power down;

DCMP Mode

Table 1.

	EQ	OUT-	OUT+
IN+ = IN-	1	0	0
IN+ < IN-	0	0	0
IN+ > IN-	0	1	1

PWM mode

For correct PWM operation CNT1/DLY1 Counter Data should be set as ‘255’.

OUT+ intended to drive a PMOS gate for pullup, while OUT- is for an NMOS gate for pulldown.

All three DCMPs/PWMs have Power option which should be turned on to enable the logic cell.

Clock invert option is used to invert internal clocking signal that is used when the DCMP/PWM uses values from its internal registers.

Output range configuration has two options: 0-99.6% and 0.39-100%. If the first option is chosen, PWM output duty cycle ranges from 0% to 99.6% and is determined as IN1/256. If the second option is chosen, PWM output duty cycle ranges from 0.39% to 100% and is determined as (IN1+1)/256.

PWM deadband is the dead time after the positive output (OUTP) falling edge or the time before the rising edge on the negative output (OUTN).

Register 0-3 are the configuration fields of the internal 8-bit register (0 is the smallest and 255 is the biggest value that can be written into the register). These 4 registers are common for all DCMP/PWM logic cells.

IN+ selector configuration is used to configure the positive input source of the DCMP/PWM logic cell. Every logic cell can be configured separately to have different sources. All DCMP/PWM logic cells have similar options of the IN+ source such as: ADC[7:0], S2P[15:8], FSM0[7:0] and additional option that concerns the internal registers. For DCMP0/PWM0 it is Register selected through matrix. For DCMP1/PWM1 it is Register 1. For DCMP2/PWM2 it is Register 0.

IN- selector configuration is used to configure the negative input source of the DCMP/PWM logic cell. Every logic cell can be configured separately to have different sources. All DCMP/PWM logic cells have similar option of the INsource: COUNTER1 (CNT1 -> Q). DCMP0/FSM0 and DCMP1/FSM1 have similar option of Register selected through matrix. DCMP2/FSM2 has Register 0 option instead.

ADC/PWM/RCO power down configuration is the same as ADC one and shares configuration options with it. To configure logic cell as DCMP simply use the ADC or S2P as positive input source and register(s) as a negative input source. To configure logic cell as PWM use the sources that changes their data value in time (Example: COUNTER1 and FSM0). If the IN+ sources from ADC and IN- sources the COUNTER1 the logic cell will operate as PWM.

If the IN- source is changed to the Register 0, the logic cell will compare the data from ADC and the data written into the Register 0 and output logic HIGH when the data from ADC is bigger than the data from the register.

In the GreenPAK2 Designer every DCMP/PWM logic cell has the following input/output nodes:

• IN-;

• IN+;

• MTRX SEL #0;

• MTRX SEL #1;

• SHARED PD;

• EQ;

• OUT-;

• OUT+;

IN- and IN+ are the negative and positive inputs respectively. They are connected automatically when the proper configuration is chosen and applied. SHARED PD is the power down node shared with ADC and RC oscillator. MTRX SEL #0, 1 are the selection nodes for DCMP/PWM internal registers. These nodes use binary code for choosing the registers:

Table 2.

MTRX SEL#1	MTRX SEL#0	Chosen register #
LOW	LOW	0
LOW	HIGH	1
HIGH	LOW	2
HIGH	HIGH	3

OUT- and OUT+ are the positive and negative non-overlapping outputs which differ on the PWM deadband value (see GreenPAK2 datasheet for better understanding of this).

EQ is an output which becomes HIGH when the two values on IN+ and IN- inputs are equal.