A D Flip Flop (DFF) captures the value of the D-input at the edge of the clock and holds the value as memory. A latch (LATCH) passes the D-input when the Clk is LOW and holds the value as memory when the Clk is HIGH. All connections are user-selected through the connection matrix and these macrocells have initial state parameters, nRESET, nSET option as well as output polarity parameters.

Parameters

Mode:

the DFF/LATCH macrocells have two modes. As a DFF or as a LATCH.

• DFF: edge triggered D Flip-Flop;

• LATCH: level triggered latch;

nSET/nRESET:

some DFFs have the option to SET/RESET. This function is active low. If no SET/RESET is desired, set this connection to VDD or a constant HIGH source.

• nRESET: if HIGH then the DFF/LATCH is in normal operation. If LOW then Q is reset to 0;

• nSET: if HIGH then the DFF/LATCH is in normal operation. If LOW then Q is set to 1;

Initial polarity:

Select the power on condition before any D-input is available. This is only effective until the first CLK input.

Q output polarity

Choose to invert or not invert output Q; nQ will be the inverse of Q.