The Pipe Delay logic cell can generate: a single delay stage on OUT0, and/or (3, 5, 7, or 11) stages of delay on OUT1, and/or (2, 4, 8, 12) stages of delay on OUT2 individually. The Pipe Delay cell is built from 12 D Flip-Flop logic cells that provide the three delay options. The DFF cells are tied in series where the output of each delay cell goes to the next DFF cell. There are delay output points for each set of the OUT1 and OUT2 outputs.

Pipe Delay cell logic cell has three inputs:

• IN – Pipe Delay input;

• CLOCK – Pipe Delay clocking signal input;

• nRESET – active LOW reset signal input;

NOTE:

Connect nRESET to any HIGH level source (VDD, POR, etc.) if it is not being used.

The Pipe Delay logic cell has three outputs:

• 1 PIPE OUT – output of one pipe;

• OUT0 – first configurable output (odd pipe numbers);

• OUT1 – second configurable output (even pipe numbers);

As the COUNTER/DELAY logic cells the Pipe Delay logic cell uses a clocking signal to control the delay time. Instead of the Counter Data it creates a pipe to generate the delay. The number of pipes used in the one channel is configured in Pipe Delay properties window of the GreenPAK2 Designer.