The Counter/Delay (CNT/DLY) is a multi-function macrocell. A CNT/DLY may be used as a: counter, delay or finite-state-machine (FSM). As a counter, the macrocell counts from the given ‘counter data’ down to zero in sync with the rising edge of a clock. The output goes from low-to-high when the ‘counter data’ is zero. As a delay, the input edge is delayed by a time equal to the ‘counter data’ multiplied by the clock period. As a finite-state-machine, the direction in which the ‘counter data’ changes can be controlled by special inputs UP/DOWN and KEEP. The ‘edge detect’ output creates a high pulse when the input edge is detected.
For more detailed information, see datasheet section 11.0 Counters/Delay Generators (CNT/DLY)
• Delay: postpones the rising and/or falling edge;
• Counter/FSM: generates a positive signal when the ‘counter data’ reaches zero;
The length of Counter/Delay period. CNT/DLY bit widths are 8-bit, from 1 to 255. For delay timing applications, it is recommended to use larger counter data values for less error.
Calculates time period with the following formulas:
• Output Period (After reset): [(Counter data + 3) / CLK input frequency];
• Output Period (All the next): [(Counter data + 1) / CLK input frequency];
• Delay time: [(Counter data + 2 + variable) / CLK input frequency] , where 0 < variable < 1;
CLK Input Frequency is the frequency of the selected Clock Source and Offset is the asynchronous time offset between the input signal and the first clock pulse.
If an input pulse is < delay time, the pulse would be filtered out. This feature can be useful for de-glitching.
In Delay or edge detect mode, select which edge to delay. In Counter Mode with Reset In, select which edge resets the counter to 0.
• Both: both rising and falling edges of pulse are delayed;
• Falling: only falling edge delayed;
• Rising: only rising edge delayed;
• High Level Reset: When RESET IN is high, counter is reset to 0;
The RESET_IN input can reset ‘counter data’ to zero or set ‘counter data’ to the the register value.
In FSM mode, the user may control the counter value using macro-cell inputs “UP, DOWN, KEEP” .
UP: macro-cell input ‘UP’ is a count direction controller. A digital high sets the FSM to count up in value. A digital low sets the FSM to count down in value and both will wrap around at 0 or maximum.
KEEP: macro-cell input ‘KEEP’ is a latching mechanism. A digital high latches the current value in FSM until ‘KEEP’ is released low. A digital low resumes normal operation where a clock input will increment or decrement its counter value.
• Counter data source: The FSM data will start at this number. When reaching 0 or max8-bit the FSM will not reload this value but instead wraps around;
Reset In resets the Counter to 0 when the RESET IN input has a valid edge. The edge is determined by the Edge select parameter. Valid in Counter Mode only.
The initial output after reset is High for the duration of one clock cycle.
ALL Counter/Delays have CLK/4/12/24/64, and an EXT CLK (from matrix). Each CNT/DLY can be sourced by another CNT/DLY (view table below).
Table 1.
| Macrocell | Bit-Width | CNT/DLY | EXT CLK |
|---|---|---|---|
| CNT/DLY0 | 8 | 8-bit CNT/DLY3 | Yes |
| CNT/DLY1 | 8 | 8-bit CNT/DLY0 | Yes |
| CNT/DLY2 | 8 | 8-bit CNT/DLY1 | Yes |
| CNT/DLY3 | 8 | 8-bit CNT/DLY2 | Yes |
Both counter and delay configurations can be sourced by an internal or external oscillator. Clock (RC OSC) without divider connections are not shown. (See OSC Info block for more information on the different CLK sources.)