Figure 1.
The Programmable Time Delay (PDLY) logic cells can generate a delay that is selectable from one of four timings (time1 in figure below) configured in the GreenPAK Designer. The programmable time delay cells can generate one of four different delay patterns, rising edge detection, falling edge detection, both edge detection and both edge delay. See the timing diagrams below for further information.
Figure 1.
Chose how the programmable delay should behave.
If ‘Both edge delay’ Mode was chosen or Output mode ‘Delayed’ was selected, use this parameter to pick the length of the delay.