The Counter/Delay (CNT/DLY) macrocell is a multi-function component. A CNT/DLY component may include the following functions: counter, delay. As a counter, the macrocell counts to the given register value and creates a pulse when it has reached the value or is reset. As a delay, it postpones rising and/or falling edges for the duration of the register value.
• Delay: postpones the rising and/or falling edge of the input signal;
• Counter/FSM: generates a positive pulse when value is reached, or when reset;
The length of Counter/Delay period. CNT/DLY bit widths are 8-bit, 1 to 255. For delay timing applications, it is recommended to use larger counter data values for less error.
Calculates time period with the following formulas:
• Output Period (After reset): [(Counter data + 3) / CLK input frequency];
• Output Period (All the next): [(Counter data + 1) / CLK input frequency];
• Delay time: [(Counter data + 2 + variable) / CLK input frequency] , where 0 < variable < 1;
CLK Input Frequency is the frequency of the selected Clock Source and Offset is the asynchronous time offset between the input signal and the first clock pulse.
If an input pulse is < delay time, the pulse would be filtered out. This feature can be useful for de-glitching.
In Delay or edge detect mode, select which edge to delay. In Counter Mode with Reset In, select which edge resets the counter to 0.
• Both: both rising and falling edges of pulse are delayed;
• Falling: only falling edge delayed;
• Rising: only rising edge delayed;
• High Level Reset: When RESET IN is high, counter is reset to 0;
For more detailed information, see datasheet section 13.1 CNT/DLY Timing Diagrams
Reset In resets the Counter to 0 when the RESET IN input has a valid edge. The edge is determined by the Edge select parameter. Valid in Counter Mode only.
The initial output after reset is High for the duration of one clock cycle.
ALL Counter/Delays have CLK/4/12/24/64, and some have EXT CLK connections. Each CNT/DLY can be sourced by another CNT/DLY (view table below).
Table 1.
| Macrocell | Bit-Width | CNT/DLY | EXT CLK |
|---|---|---|---|
| CNT/DLY0 | 8 | 8-bit CNT/DLY3 | Yes |
| CNT/DLY1 | 8 | 8-bit CNT/DLY0 | Yes |
| CNT/DLY2 | 8 | 8-bit CNT/DLY1 | Yes |
| CNT/DLY3 | 8 | 8-bit CNT/DLY2 | No |
Both Counter and Delay configurations can be sourced by an internal or external oscillator. Clock (RC OSC) without divider connections are not shown. (See OSC Info block for more information on the different CLK sources.)