The Power On Reset (POR) macrocell will produce a logic HIGH signal as an output when the device power supply (VDD) rises to approximately 1.4 V and device completely starts up. The internal blocks by default have initial LOW level. All outputs are in Hi-Z state and chip starts loading data from NVM. The reset signal is released for internal blocks and they start to initialize according to the following sequence:

• Input PINs, pull up/downs;

• LUTs;

• DFFs, Delays/Counters, Pipe Delay;

• POR output to matrix;

• Output PIN corresponds to the internal logic;

The POR signal going HIGH indicates the mentioned powerup sequence is complete.

Description

The POR block is used internally to make guarantees for startup conditions regardless of the condition at the input. DLY cells will pass their inputs through during the startup sequence without delaying the signal per the configuration, so a LUT added in front of the input of a DLY that ANDs the DLY input with POR will guarantee the input signal will not appear until the chip has fully powered up and will enforce delays.

Note

The maximum voltage applied to any PIN should not be higher than the VDD level. There are ESD Diodes between PIN –> VDD and PIN –> GND on each PIN. So if the input signal applied to the PIN is higher than VDD, then current will sink through the diode to VDD. Exceeding VDD results in leakage current on the input PIN, and VDD will be pulled up, following the voltage on the input PIN.

There is no effect from input PIN when input voltage is applied at the same time as VDD.

During power down, blocks in GreenPAK3 are powered off and logic blocks may switch states after falling below 1.4 V. The I/O buffers are disabled when POR goes LOW at VDD~1 V. Please note that during a slow ramp down, outputs can possibly switch state.