The Pipe Delay is a 16 stage delay composed of 16 DFFs. Three inputs from the matrix, Input (IN), Clock (CLK) and Reset (RST) control Pipe Delay behavior. The two outputs (OUT0 and OUT1) provide user selectable options for 1 – 16 stages of delay while 1 PIPE OUT is always connected to the first delay stage.
For correct Pipe Delay functionality nReset (nRST) input should be HIGH. If nReset (nRST) input is LOW the Pipe Delay is in a reset state and all outputs are LOW.
The pipe delay cell is built from 16 D Flip-Flop logic cells that provide two delay options which are user selectable. The DFF cells are tied in series where the output (Q) of each delay cell goes to the next DFF cell. There are delay output points for each set of the OUT0 and OUT1 outputs to a 4-input mux that is controlled by register bits. The 4-input mux is used to control the selection of the amount of delay. The overall time of the delay is based on the clock used in the block.
The pipe delay can be configured as a clock divider by setting OUT1’s output polarity to be negative and feeding nOUT1 into IN. The divider will be 2x the register value chosen in OUT1 PD num for a max divider of 32.
1-16 Choose the number of CK rising edges before the IN propagates to OUT0;
1-16 Choose the number of CK rising edges before the IN propagates to OUT1;
• Non-inverted(OUT1);
• Inverted (nOUT1);
If RCOSC is used as the CK input, then RC OSC power may need to be set as “Forced” in the properties menu as it will not be triggered by “Auto power” from Pipe Delay only.