Figure 1.
The PAK4 OSC block has three internal clock sources: RC, Low frequency (LF) and Ring, which can be used independently and simultaneously. RC Oscillator can be either 25 kHz or 2 MHz (user select-able); LF oscillator is 1.6 kHz and the Ring oscillator is 25 MHz. External clock sources can also be used as an input frequency source to the OSC block.
Many clocking connections in the GPAK4 are hardwired. These connections are enabled by the settings of a block’s properties. In the schematic view, non-default hardwired connections appear as orange wires. RC OSC with no divider does not show a visible connection wire, as it is the default clocking connection.
External clocking:
Matrix signals can be routed through the OSC block via EXT_CLK0 or EXT_CLK1 to the clock input of the DLY/CNT.
If the oscillator PWR DOWN input is LOW, the oscillator will be turned on. If PWR DOWN input of the oscillator is HIGH, the oscillator will be turned off.
The internal oscillator can dynamically cycle power based on the needs of the delay blocks. The below figure shows how the OSC turns on whenever a signal on the DLY block arrives and runs until the delay is completed (marked by the rise in DLY_OUT). The clock then Powers down until it needs to clock the delay for the falling edge and powers back up. Once the delay for the falling edge is completed, the clock powers down once again. It is important to note that CNT blocks do not cause the clock to Power up, in which case the OSC power mode should be set to Force power on.
Figure 1.
• Auto power on: will automatically Power down and Power up the OSC. See Auto power on above;
• Force power on: will run the OSC continuously;
This cannot be changed, but simply shows the LF OSC frequency.
When the power down signal is HIGH, the OSC will turn off and minimize current consumption
• Enable: will allow the Power Down input of the OSC to power down the LF OSC;
• Disable: will ignore the logic at the Power Down input of the OSC;
a divider internal to the OSC block.
Clock output configurations are shown in the table below the properties.
• LF OSC;
• EXT. CLK0;
• Auto power on: will automatically ower down and Power up the OSC. See Auto power on above;
• Force power on: will run the OSC continuously;
The RC OSC can be set to the following two frequencies.
• 25kHz;
• 2000kHz;
When the power down signal is HIGH, the OSC will turn off and minimize current consumption
• Enable: will allow the Power down input to the OSC to power down the RC OSC;
• Disable: will ignore the logic at the PowerdDown input of the OSC;
a divider internal to the OSC block that divides the selection from Clock selector (below).
gates the signal OUT0 from the OSC block to the connection matrix. This setting is changed by connecting OUT0 to a matrix input.
• Enable: will pass the clock signal onto the matrix;
• Disable: will keep OUT0 LOW;
Additional division after the predivider.
Muxes between RC OSC and Ext. CLK0.
• RC OSC: internal oscillator;
• EXT. CLK0: is an input pin to the OSC. It can be configured from any matrix connection;
• Auto power on: will automatically power down and power up the OSC. See Auto-power on above;
• Force power on: will run the OSC continuously;
This cannot be changed, but simply shows the Ring OSC frequency.
When the power down signal is HIGH, the OSC will turn off and minimize current consumption
• Enable: will allow the Power Down input to the OSC to power down the Ring OSC;
• Disable: will ignore the logic at the Power Down input of the OSC;
a divider internal to the OSC block that divides the selection from Clock selector (below).
gates the signal OUT1 from the OSC block to the connection matrix. This setting is changed by connecting OUT1 to a matrix input.
• Enable: will pass the clock signal onto the matrix;
• Disable: will keep OUT1 LOW;
Additional division after the predivider.