The Oscillator (OSC) macrocell is the main hub for providing clock sources to the connection matrix and special components (CNT/DLY, DCMP, SPI and ADC). There are three types of internal clock sources: RC, Low frequency (LF) and Ring. RC oscillator is 25 kHz or 2 MHz, LF oscillator is 1.6 kHz and the Ring oscillator is 25 MHz. All three sources are independent and can be used simultaneously. Another option is to use external clocks which can be sourced from a GPIO or matrix signals.

See Datasheet Section 21.0 Oscillators for more information

Description

The faster the frequency, the higher the current consumption and the slower frequencies will have lower current consumption.

All CNT/DLY, DCMP, SPI and ADC Clock Source connections are hardwired. Complete the connections by selecting the desired clock source from the CNT/DLY, DCMP, SPI and ADC macrocell. RC OSC w/o divider does not show a connection wire in GPAK Designer, however, other wires will be shown when the connection is made.

Use other clock signals by routing them through the oscillator block via the EXT CLK inputs. EXT CLK0,1,4 are located in matrix 0 while EXT. CLK2,3 are in matrix 1.

DLY/CNT blocks can be clocked by a limited number of EXT. CLK signals depending on the DLY/CNT block (see table). To route a matrix signal to the clock of a DLY/CNT, determine which EXT. CLKs it can accept and route the matrix output to that EXT. CLK input on the OSC.

Table 1. EXT CLKs

Block Matrix EXT. CLK0 EXT. CLK1 EXT. CLK2 EXT. CLK3 EXT. CLK4

CNT0/DLY0 0 +

CNT1/DLY1 1 +

CNT2/DLY2/FSM0 0 + +

CNT3/DLY3 1 +

CNT4/DLY4/FSM1 1 + + +

CNT5/DLY5 0 +

CNT6/DLY6 0 +

CNT7/DLY7 1 +

CNT8/DLY8 1 + + +

CNT9/DLY9 0 + +

Block	Matrix	EXT. CLK0	EXT. CLK1	EXT. CLK2	EXT. CLK3	EXT. CLK4
CNT0/DLY0	0	+
CNT1/DLY1	1				+
CNT2/DLY2/FSM0	0	+				+
CNT3/DLY3	1				+
CNT4/DLY4/FSM1	1	+			+	+
CNT5/DLY5	0		+
CNT6/DLY6	0		+
CNT7/DLY7	1			+
CNT8/DLY8	1	+		+		+
CNT9/DLY9	0	+				+

Activation

If PWR DOWN input the oscillator is LOW, the oscillator will be turned on. If PWR DOWN input of the oscillator is HIGH, the oscillator will be turned off.

Auto power on

The internal oscillator can dynamically cycle power based on the needs of the delay blocks. The below figure shows how the OSC turns on whenever a signal on the DLY block arrives and runs until the delay is completed (marked by the rise in DLY_OUT). The clock then powers down until it needs to clock the delay for the falling edge and powers back up. Once the delay for the falling edge is completed, the clock powers down once again. It is important to note that CNT blocks do not cause the clock to power up, in which case the OSC Power mode should be set to Force power on.

Figure 1.

Parameters (LF OSC)

LF OSC power mode:

• Auto power on: will automatically power down and power up the OSC. See Auto power on above;

• Force power on: will run the OSC continuously;

LF OSC frequency:

This cannot be changed, but simply shows the LF OSC frequency.

LF matrix power down:

When the power down signal is HIGH, the OSC will turn off and minimize current consumption

• Enable: will allow the Power Down input of the OSC to power down the LF OSC;

• Disable: will ignore the logic at the Power Down input of the OSC;

LF Clock predivider by:

a divider internal to the OSC block.

Clock selector:

Clock output configurations are shown in the table below the properties.

• LF OSC;

• EXT. CLK0;

Parameters (RC OSC)

RC OSC power mode:

• Auto power on: will automatically Power down and Power up the OSC. See Auto power on above;

• Force power on: will run the OSC continuously;

RC OSC frequency:

The RC OSC can be set to the following two frequencies.

• 25kHz;

• 2000kHz;

RC Matrix power down:

When the Power down signal is HIGH, the OSC will turn off and minimize current consumption

• Enable: will allow the Power down input to the OSC to Power down the RC OSC;

• Disable: will ignore the logic at the Power down input of the OSC;

RC CLK predivider by:

a divider internal to the OSC block that divides the selection from Clock selector (below).

RC Clock to matrix input enable:

gates the signal OUT0 from the OSC block to the connection matrix. This setting is changed by connecting OUT0 to a matrix input.

• Enable: will pass the clock signal onto the matrix;

• Disable: will keep OUT0 LOW;

‘OUT0’ second divider by:

Additional division after the predivider.

Clock selector:

Muxes between RC OSC and Ext. CLK0.

• RC OSC: internal oscillator;

• EXT. CLK0: is an input pin to the OSC. It can be configured from any matrix connection;

Parameters (RING OSC)

Ring OSC Power Mode:

• Auto power on: will automatically Power down and Power up the OSC. See Auto power on above;

• Force power on: will run the OSC continuously;

Ring OSC frequency:

This cannot be changed, but simply shows the Ring OSC frequency.

Ring Matrix power down:

When the Power down signal is HIGH, the OSC will turn off and minimize current consumption

• Enable: will allow the Power down input to the OSC to Power down the Ring OSC;

• Disable: will ignore the logic at the Power down input of the OSC;

Ring clock predivider by:

a divider internal to the OSC block that divides the Ring clock

Ring clock to matrix input enable:

gates the signal OUT1 from the OSC block to the connection matrix. This setting is changed by connecting OUT1 to a matrix input.

• Enable: will pass the clock signal onto the matrix;

• Disable: will keep OUT1 LOW;

‘OUT1’ second divider by:

Additional division after the predivider.