The Power On Reset (POR) macrocell will produce a logic HIGH signal as an output when the device power supply (VDD) rises to approximately 1.4 V and device completely starts up. The internal blocks by default have initial LOW level. All outputs are in Hi-Z state and chip starts loading data from NVM. The reset signal is released for internal blocks and they start to initialize according to the following sequence:

• Input PINs, pull up/downs;

• LUTs;

• DFFs, Delays/Counters, Pipe Delay;

• POR output to matrix;

• Output PIN corresponds to the internal logic;

The POR signal going HIGH indicates the mentioned powerup sequence is complete.

Description

The POR block is used internally to make guarantees for startup conditions regardless of the condition at the input. DLY cells will pass their inputs through during the startup sequence without delaying the signal per the configuration, so a LUT added in front of the input of a DLY that ANDs the DLY input with POR will guarantee the input signal will not appear until the chip has fully powered up and will enforce delays.

Parameters

Chip power on delay:

This adds an extra delay to the POR signal after internal blocks have been powered.

• 4 µs;

• 500 µs;