The Counter/Delay (CNT/DLY) is a multi-function component. A CNT/DLY component may include the following functions: counter, delay, finite state machine (FSM), edge detector, or wake-sleep controller (WS Ctrl). As a counter, the macrocell counts to the given register value and creates a pulse when it has reached the value or is reset. As a delay, it postpones rising and/or falling edges for the duration of the register value. As a finite state machine, the counter’s data can be manipulated up or down. As an edge detector, the macrocell generates a pulse on a rising and/or falling edge. As a Wake-Sleep controller, the macrocell controls the power up/down of analog blocks ADC and ACMP.
• Delay: postpones the rising and/or falling edge of the input signal;
• Counter/FSM: generates a positive pulse when value is reached, or when reset;
• Edge detect: generates a pulse on a rising and/or falling edge;
The length of Counter/Delay period. CNT/DLY bit widths are 14-bit or 8-bit, from 1 to 16383 or 1 to 255 respectively. For delay timing applications, it is recommended to use larger counter data values for less error.
Calculates time period with the following formulas:
• Output period: [(Counter data + 1) / CLK input frequency – Offset];
• Delay time: [(Counter data + 2) / CLK input frequency – Offset];
CLK Input Frequency is the frequency of the selected Clock Source and Offset is the asynchronous time offset between the input signal and the first clock pulse.
If an input pulse is < delay time, the pulse would be filtered out. This feature can be useful for de-glitching.
In Delay or edge detect mode, select which edge to delay. In Counter Mode with Reset In, select which edge resets the counter to 0.
• Both: both rising and falling edges of pulse are delayed;
• Falling: only falling edge delayed;
• Rising: only rising edge delayed;
• High Level Reset: When RESET IN is high, counter is reset to 0;
The Q mode selects the reset function for a counter/FSM when the data wraps around at 0 or max value. Set would load the counter/FSM data from a source, and Reset would load a zero.
• Set: loads either the design counter data, ADC data, or SPI data. Source data is selectable through the parameter ‘FSM data’ under ‘Connections’;
• Reset: loads 0;
For more detailed information, see datasheet section 14.1.2 Counter Mode
In FSM mode, the user may control the counter value using macro-cell inputs “UP, DOWN, KEEP” .
UP: macro-cell input ‘UP’ is a count direction controller. A digital high sets the FSM to count up in value. A digital low sets the FSM to count down in value and both will wrap around at 0 or maximum.
KEEP: macro-cell input ‘KEEP’ is a latching mechanism. A digital high latches the current value in FSM until ‘KEEP’ is released low. A digital low resumes normal operation where a clock input will increment or decrement its counter value.
• Counter data source: The FSM data will start at this number. When reaching 0 or max16-bit the FSM will not reload this value but instead wraps around;
For more detailed information, see datasheet section 14.1.3 FSM Mode
Use WS Ctrl for controlling the power on and power off of analog blocks ACMP and ADC. WS Ctrl frequency is sourced by the LF OSC. The sleep will turn off the regulator and bandgap.
Enable/Disable this wake sleep control to ALL ACMPs. ACMP PWR UP has highest priority.
Enable/Disable this wake sleep control to ADC. ADC PWR DN has highest priority.
When the LF OSC is powered down, chose whether the Analog Blocks stay in sleep mode or wake mode.
• Force sleep (LOW): when LF OSC is powered down;
• Force wake (HIGH): when LF OSC is powered down;
Reset In resets the Counter to 0 when the RESET IN input has a valid edge. The edge is determined by the Edge select parameter. Valid in Counter Mode only.
The initial output after reset is High for the duration of one clock cycle.
All Counter/Delays have CLK/4/12/24/64, Ring OSC, LFOSC, ADC_CLK/256, EXT CLK connections. Each CNT/DLY can be sourced by another CNT/DLY (view table below).
Table 1.
| Macrocell | Matrix | Bit-Width | CLK/12 | ADC CLK | EXT CLK | CNT/DLY |
|---|---|---|---|---|---|---|
| CNT/DLY0 | 0 | 14 | EXT. CLK0 | 8-bit CNT/DLY9 | ||
| CNT/DLY1 | 1 | 14 | EXT. CLK3 | 14-bit CNT/DLY0 | ||
| CNT/DLY2 | 0 | 14 | CLK/12 | ADC CLK | EXT. CLK0 | 14-bit CNT/DLY1 |
| ADC CLK/256 | EXT. CLK0/8 | |||||
| EXT. CLK4 | ||||||
| CNT/DLY3 | 1 | 14 | EXT. CLK3 | 14-bit CNT/DLY2 | ||
| CNT/DLY4 | 1 | 8 | CLK/12 | ADC CLK | EXT. CLK3 | 14-bit CNT/DLY3 |
| ADC CLK/256 | EXT. CLK3/8 | |||||
| EXT. CLK4 | ||||||
| CNT/DLY5 | 0 | 8 | EXT. CLK1 | CNT/DLY4 | ||
| CNT/DLY6 | 0 | 8 | EXT. CLK1 | CNT/DLY5 | ||
| CNT/DLY7 | 1 | 8 | EXT. CLK2 | CNT/DLY6 | ||
| CNT/DLY8 | 1 | 8 | CLK/12 | ADC CLK | EXT. CLK2 | CNT/DLY7 |
| ADC CLK/256 | EXT. CLK2/8 | |||||
| EXT. CLK4 | ||||||
| CNT/DLY9 | 0 | 8 | CLK/12 | ADC CLK | EXT. CLK0 | CNT/DLY8 |
| ADC CLK/256 | EXT. CLK0/8 | |||||
| EXT. CLK4 |
Both counter and delay configurations can be sourced by an internal or external oscillator. Clock (RC OSC) without divider connections are not shown. (See OSC Info block for more information on the different CLK sources.)