A Serial to Parallel Interface (SPI) block can be configured in one of two modes: Serial to Parallel (S2P) or Parallel to Serial (P2S). In S2P mode, SPI will convert 2-bytes of serial data into a 2-byte parallel bus. In P2S mode, SPI will convert a 2-byte parallel bus into 2-bytes of serial data. The Inputs are standard SPI I/O connections (MOSI, MISO, nCSB, SCLK, and OUTs).

The INTR (Interrupt) output goes HIGH on the last clock once the Parallel Data in P2S mode has been fully clocked out.

S2P activation

Remove the connection of VDD to the nCSB input.
MOSI connection: Set PIN10 mode to Digital Input and select SPI <- PIN10 (out) for the ‘Serial data’ connection parameter. An orange wire will show denoting the connection.
Connect both the nCSB and SCLK to either the matrix or PINs.
See the ‘Connection’ section for PAR_OUT connections.

P2S activation

Remove the connection of VDD to the nCSB input.
MISO connection: Set PIN10 mode to Digital Output and select ADC -> PIN10(in) for the ‘Serial data’ connection parameter. An orange wire will show denoting the connection.
PAR_IN connection: Select FSM0/FSM1 or ADC as the ‘PAR Input data source’ connection parameter.
Connect both the nCSB and SCLK to either the matrix or PINs.

Parameters

Mode:

The SPI block can either convert from Serial to Parallel or Parallel to Serial.

• S2P: The SPI block will convert Serial data into Parallel data;

• P2S: The conversion is from Parallel data to Serial;

Clock phase (CPHA):

The Clock phase determines which edge the data starts sampling at.

• 0: the SPI samples on the first edge;

• 1: the SPI samples on the second edge;

Clock polarity (CPOL):

The Clock polarity determines the base value of the clock

• 0: clock has a base value of 0;

• 1: clock has a base value of 1;

Byte selection:

Choose the number of bytes to input or output from the SPI block

ADC data sync with SPI clock:

ADC parallel output will be synced to SPI Parallel Input even if ADC and SPI do not have the same Clk source.

PWM data sync with SPI clock:

PWM parallel output will be synced to SPI Parallel Input even if PWM and SPI do not have the same Clk source.

FSM data sync with SPI clock:

FSM parallel output will be synced to SPI Parallel Input even if FSM and SPI do not have the same Clk source.

Connections

PAR_IN and Serial in and Serial out connections can be configured here. PAR_OUT is configured at the receiving block. To configure PAR_OUT connections, go to either the FSM0, DCMP or DACs and choose SPI[15:8] or SPI[7:0] as the parallel input source.

In order to have the SPI block drive the DACs, the DAC must be configured as having the same input source as DCMP1 and the DCMP1 must have the SPI connection as its input source.

PAR input data source:

The parallel input is multiplexed between FSM0/FSM1 and ADC. FSM0 is the low byte and FSM1 is the high byte.

• FSM0[7:0] FSM1[7:0];

• ADC;

Serial data out:

The serial output line is multiplexed between the SPI and ADC serial outputs. Only one connection is available at a time.

• Disable (Matrix -> PIN10 (in)): the connection is disabled between PIN10 and the serial output connections. The PIN10 (in) can be connected from the matrix;

• SPI -> PIN10 (in): The serial output of the SPI is connected to PIN10. PIN10 needs to be configured as a Digital output;

• ADC -> PIN10 (in): The serial output of the ADC is connected to PIN10. PIN10 needs to be configured as a Digital output;

INTR:

The interrupt pin is only active in the P2S mode. On the falling edge of the last clock 8-th or 16-th clock, the interrupt pin will be HIGH for 1 clock cycle. If the polarity is set to CPOL enabled, the interrupt pin will begin on the rising edge of the clock.

nCSB:

nCSB is an active low chip select. If nCSB is low, the SPI block is enabled.

SCLK:

SCLK is the serial clock which clocks the SPI block.