The I2C Serial Communication Block (I2C) slave macrocell is accessed through SDA and SCL buses on PIN 6 and PIN 7. These pins are pure Open Drain NMOS and can be pulled above VDD. The Control Code is a 4-bit address ranging from 0 to 15. The I2C macrocell has 8 register outputs (I2C Virtual Inputs) and 8 dedicated 8-bit memory arrays (RAM Array Table).
For more information on I2C Serial Communication Block, see Datasheet Section 19.0 I2C Serial Communication Block or App Note AN-1090
To active I2C, set ‘Power control’ to Enable. To deactivate I2C, set ‘Power control’ to Disable.
Enable or Disable the I2C Macro-cell.
• Enable: PIN 6 and PIN 7 are connected to the SDA and SCL inputs of the I2C macrocell.
• Disable: PIN 6 and PIN 7 are disconnected and can be used as GPIOs
This register reg<1663> is one the configurations that cannot be written with I2C write. Therefore, emulation will not be able to write this configuration. Program the device to set this register to a 1.
If IO Latching is Enabled, the GPIO outputs will be held logic 1 or logic 0 during I2C activity, however configuration bits will still update at the end of each acknowledge.
For an I2C Read, the GPIOs are Latched from Start bit to the end of the Slave Address.
For an I2C Write, the GPIOs are Latched from Start bit to the Stop Bit.
If IO Latched is Disabled, the GPIO outputs will not be held at a logic high or low. Configuration bits will update at the end of each Acknowledge.
This is one of the configurations that cannot be written with I2C. Therefore these registers cannot be emulated, only programmed.
In the control byte, bits [6:3] are used to address the PAK device. By changing those four bits, the possible binary values are 0000b..1111b. This way the I2C Master can control up to 16 I2C slaves individually.
The I2C Virtual Inputs can be configured with an initial value upon power up.
Each Byte from the RAM Array (Bytes at location 0xD8 through 0xDF) can be configured with an initial decimal byte value upon power up.