PAK5 has two independent Oscillator macro-cells OSC0 and OSC1. The internal frequencies are 25 kHz, 2 MHz and 25MHz. The external clock inputs are PIN 14 and PIN 13. The Oscillator block generates clock signals used by the CNT/DLY blocks and some are connected to the connection matrix. The higher the frequency, the higher the current consumption.

Description

OSC0 is configurable to 25 kHz, 2 MHz or external PIN 14. OSC1 is configurable to 25 MHz or external PIN 13. Both oscillator blocks have forced power on and auto-power on capabilities. Force Power Down only applies to internal oscillators.

The orange clock lines (Clk/4, CLK/64 etc) are clock connections which do not enter the connection matrix. These lines are activated through a CNT/DLY block’s clock source parameter.
The only clock line not shown is Clk/1.

Activation

For “control pin mode: power down”, PWR DOWN input must be LOW.
For “control pin mode: Force on”, PWR DOWN input can be HIGH or LOW.

Auto power on

The internal oscillator can dynamically cycle power based on the needs of the delay blocks. In this mode, the OSC turns on whenever an edge signal on the DLY block arrives and runs until the delay is completed. It is important to note that CNT blocks do not cause the clock to power up, in which case the OSC Power mode should be set to Force power on.

Parameters

Control pin mode:

When the Power down control pin is HIGH, the OSC will turn off and minimize current consumption

• Power down: PWR DOWN must be LOW to leave OSC controlled by OSC Power Mode, while HIGH will turn off the OSC.

• Force on: FORCE ON must be HIGH to force on the OSC and LOW to leave OSC controlled by OSC Power Mode.

OSC power mode:

• Auto power on: Allow DLY blocks to turn OSC on and off. Will have an extra power on delay.

• Force power on: OSC always on;

Clock selector:

Select Internal or External Clock.

• OSC;

• EXT CLK;

EXT CLK Pin selector:

• OSC0: PIN 14

• OSC1: PIN 13

Fast start-up (OSC0 only):

• Disable: A few uS to a half cycle delay before OSC0 Starts up.

• Enable: Less start-up delay. Consumes additional power. (700nA at 5.0V VDD).

RC OSC frequency:

The RC OSC can be set to generate different frequencies. OSC0 has 25kHz and 2000kHz. OSC1 has 25 MHz.

CLK predivider:

A divider within the OSC block that alters the clock’s frequency. Possible options are /1, /2, /4, /8.

‘OUTx’ second divider (OSC0 only):

In OSC0, OUTx has an additional dividing stage. Possible options are /1, /2, /3, /4, /8, /12, /24, /64.