// A/B stage

MODEM_1_3V == !SEL_Q ? MODEM_A_3V : MODEM_B_3V;
MODEM_1_1V8 == !SEL_Q ? MODEM_A_1V8 : MODEM_B_1V8;
MODEM_2_3V == SEL_Q ? MODEM_A_3V : MODEM_B_3V;
MODEM_2_1V8 == SEL_Q ? MODEM_A_1V8 : MODEM_B_1V8;

CPU_1_3V == !SEL ? CPU_PWR_EN && CPU_3V_n1V8 : 0;
CPU_1_1V8 == !SEL ? CPU_PWR_EN && !CPU_3V_n1V8 : 0;
CPU_2_3V == SEL ? CPU_PWR_EN && CPU_3V_n1V8 : 0;
CPU_2_1V8 == SEL ? CPU_PWR_EN && !CPU_3V_n1V8 : 0;

// Modem/CPU stage

VSEL_1_3V == CPU_1_3V || MODEM_1_3V;
VSEL_1_EN == VSEL_1_3V || SWP_1 || CPU_1_1V8 || MODEM_1_1V8;
VSEL_2_3V == CPU_2_3V || MODEM_2_3V;
VSEL_2_EN == VSEL_2_3V || SWP_2 || CPU_2_1V8 || MODEM_2_1V8;