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authorWerner Almesberger <werner@almesberger.net>2016-10-29 17:15:39 (GMT)
committerWerner Almesberger <werner@almesberger.net>2016-10-29 17:15:39 (GMT)
commit55a6061143b2dddc336c5a5c0a2fa6d406ebc00a (patch)
tree42d28b9fd02e8932a455a5e8456b8440b8e08fe7 /ir
parent527774d5827d8cb7c4e396a3e876734df5f4bf38 (diff)
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ir/ir.tex, rx.fig: bring back the analog switch
This largely reverts 0899d39abd262c847a0c6be90361c8de3dadc77a
Diffstat (limited to 'ir')
-rw-r--r--ir/ir.tex13
-rw-r--r--ir/rx.fig31
2 files changed, 31 insertions, 13 deletions
diff --git a/ir/ir.tex b/ir/ir.tex
index 5725e7e..c0c16f4 100644
--- a/ir/ir.tex
+++ b/ir/ir.tex
@@ -776,22 +776,29 @@ The following diagram shows the IR receiver circuit:
\includegraphics[scale=0.89]{rx.pdf}
\end{center}
-D1 is reverse-biased through R6.
+When the receiver is enabled (analog switch U2 is closed), D1 is
+reverse-biased through R6.
R6 pulls the signal at {\bf B} close to ground when the diode is not
illuminated, and lets the voltage raise when D1 is illuminated and
the reverse current through it increases.
The high-pass filter is implemented by comparing the signal from the
-sensor ({\bf B}) with the same signal after passing the
+sensor ({\bf B} and {\bf C}) with the same signal after passing the
low-pass filter formed by R5 and C1 ({\bf A}).
When the diode is not illuminated, R5 also ensures that the voltage
-at {\bf A} is higher than at {\bf B}, thus adding a threshold for
+at {\bf A} is higher than at {\bf C}, thus adding a threshold for
signal detection.
The comparator U1 operates as inverting Schmitt-trigger, with
R1 and R2 determining the hysteresis.
+When the receiver is disabled (analog switch U2 is open) and the
+sensor is not illuminated,
+the voltage divider formed by R3 and R4 (with some contribution
+from R1) lets C1 charge to the expected operating point.
+R6 pulls {\bf C} to ground in this case.
+
R7 ensures that CPU and Hackerbus can override the IR receiver,
especially when disabled or not illuminated.
diff --git a/ir/rx.fig b/ir/rx.fig
index 9d93b08..f45aa25 100644
--- a/ir/rx.fig
+++ b/ir/rx.fig
@@ -7,15 +7,15 @@ A4
Single
-2
1200 2
-6 4410 6570 4995 7470
+6 7695 6570 8280 7470
2 2 0 3 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
- 4500 6615 4680 6615 4680 7020 4500 7020 4500 6615
+ 7785 6615 7965 6615 7965 7020 7785 7020 7785 6615
2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
- 4590 7020 4590 7425
+ 7875 7020 7875 7425
2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
- 4455 7425 4725 7425
-4 0 0 50 -1 22 12 0.0000 4 135 210 4725 6795 R6\001
-4 0 0 50 -1 22 12 0.0000 4 135 270 4725 7020 22k\001
+ 7740 7425 8010 7425
+4 0 0 50 -1 22 12 0.0000 4 135 210 8010 6795 R6\001
+4 0 0 50 -1 22 12 0.0000 4 135 270 8010 7020 22k\001
-6
2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
7245 4635 5175 4635
@@ -34,7 +34,7 @@ Single
2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
8415 5445 8595 5445
2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
- 8325 5445 7875 5445 7875 6300 4590 6300
+ 8325 5445 7875 5445 7875 6300 6570 6300
2 2 0 3 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
7245 4545 7650 4545 7650 4725 7245 4725 7245 4545
2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
@@ -90,9 +90,16 @@ Single
2 2 0 3 0 7 50 -1 -1 0.000 0 0 7 0 0 5
10125 4950 10530 4950 10530 5130 10125 5130 10125 4950
2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
- 4590 4500 4590 6615
-2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
8865 6075 8865 5445
+2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 0 0 4
+ 4590 4500 4590 6300 6300 6300 6525 6210
+2 2 0 3 0 7 50 -1 -1 0.000 0 0 -1 0 0 5
+ 6210 6075 6660 6075 6660 6525 6210 6525 6210 6075
+2 1 0 3 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
+ 6435 6975 6435 6525
+3 2 0 3 0 7 50 -1 -1 0.000 0 0 0 2
+ 7875 6300 7875 6615
+ 0.000 0.000
4 0 0 50 -1 22 12 0.0000 4 135 210 8955 4635 U1\001
4 1 0 50 -1 22 12 0.0000 4 135 120 6300 4590 A\001
4 0 0 50 -1 22 12 0.0000 4 135 270 7245 4500 33k\001
@@ -116,5 +123,9 @@ Single
4 0 0 50 -1 22 12 0.0000 4 135 210 4320 4230 D1\001
4 2 0 50 -1 22 12 0.0000 4 135 1020 4500 4725 VEMD10940F\001
4 2 0 50 -1 22 12 0.0000 4 135 1005 4095 5445 Audio codec\001
-4 1 0 50 -1 22 12 0.0000 4 180 645 8910 6255 GPIO.bq\001
4 1 0 50 -1 22 12 0.0000 4 135 120 4950 6255 B\001
+4 1 0 50 -1 22 12 0.0000 4 180 645 8865 6255 GPIO.bq\001
+4 1 0 50 -1 22 12 0.0000 4 135 210 6435 6030 U2\001
+4 1 0 50 -1 22 12 0.0000 4 180 645 6435 7155 GPIO.bq\001
+4 0 0 50 -1 22 12 0.0000 4 135 810 6525 6750 NX3V1G66\001
+4 1 0 50 -1 22 12 0.0000 4 135 120 7875 5400 C\001